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NEC_V.inc@ 630

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Last change on this file since 630 was 630, checked in by Krister Nordvall, 8 days ago

Changes:

Changed the g_szPCFlashSuccessful string in XTIDECFG to reflect the reality - it turns out ANY key was limited to just ENTER or ESC.
Removed the NEC V-specific optimization I added in r602 because NEC's documentation completely fails to mention that the ROL4 instruction also changes the high nibble of AL. Huge thanks to vcfed-member dreNorteR for discovering this and also for suggesting an optimization to the physical address conversion code in IdeTransfer.asm.
Made some changes to the OUTPUT_AL_TO_IDE_REGISTER and OUTPUT_AL_TO_IDE_CONTROL_BLOCK_REGISTER macros as an optimization. This saves 15+12 bytes in builds without MODULE_8BIT_IDE (e.g. the PS/2 builds).
Other minor optimizations and cleanups.

File size: 24.8 KB

Line
1	; Project name : Assembly Library
2	; Description : Macros for using NEC V20/V30 specific instructions.
3
4	;
5	; XTIDE Universal BIOS and Associated Tools
6	; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2024 by XTIDE Universal BIOS Team.
7	;
8	; This program is free software; you can redistribute it and/or modify
9	; it under the terms of the GNU General Public License as published by
10	; the Free Software Foundation; either version 2 of the License, or
11	; (at your option) any later version.
12	;
13	; This program is distributed in the hope that it will be useful,
14	; but WITHOUT ANY WARRANTY; without even the implied warranty of
15	; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16	; GNU General Public License for more details.
17	; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
18	;
19
20	%ifndef NEC_V_INC
21	%define NEC_V_INC
22
23	regAL equ 000b
24	regCL equ 001b
25	regDL equ 010b
26	regBL equ 011b
27	regAH equ 100b
28	regCH equ 101b
29	regDH equ 110b
30	regBH equ 111b
31
32	regAX equ regAL
33	regCX equ regCL
34	regDX equ regDL
35	regBX equ regBL
36	regSP equ regAH
37	regBP equ regCH
38	regSI equ regDH
39	regDI equ regBH
40
41
42	;--------------------------------------------------------------------
43	; The REPC string instruction prefix available on NEC V20/V30 CPUs.
44	;
45	; Repeats the following string instruction (CMPS or SCAS)
46	; while CF=1 and CX<>0.
47	;
48	; eREPC
49	; Parameters:
50	; %1: String instruction (optional for this macro)
51	; CX: String length in BYTEs or WORDs
52	; xS:SI: Pointer to source string. Default segment is DS but can be overridden
53	; ES:DI: Pointer to destination string
54	; Returns:
55	; CF/CX: Depends on the result from the string instruction.
56	; If CF clear, then CX contains the remaining number of
57	; BYTEs or WORDs in the string. If CF set, then CX=0.
58	; SI/DI: Updated depending on the string instruction used and
59	; state of the direction flag.
60	; Corrupts registers:
61	; The string instruction corrupts FLAGS. The prefix corrupts nothing.
62	;--------------------------------------------------------------------
63	%macro eREPC 0-1.nolist
64	db 65h
65	%ifnempty %1
66	%1
67	%endif
68	%endmacro
69
70
71	;--------------------------------------------------------------------
72	; The REPNC string instruction prefix available on NEC V20/V30 CPUs.
73	;
74	; Repeats the following string instruction (CMPS or SCAS)
75	; while CF=0 and CX<>0.
76	;
77	; eREPNC
78	; Parameters:
79	; %1: String instruction (optional for this macro)
80	; CX: String length in BYTEs or WORDs
81	; xS:SI: Pointer to source string. Default segment is DS but can be overridden
82	; ES:DI: Pointer to destination string
83	; Returns:
84	; CF/CX: Depends on the result from the string instruction.
85	; If CF set, then CX contains the remaining number of
86	; BYTEs or WORDs in the string. If CF clear, then CX=0.
87	; SI/DI: Updated depending on the string instruction used and
88	; state of the direction flag.
89	; Corrupts registers:
90	; The string instruction corrupts FLAGS. The prefix corrupts nothing.
91	;--------------------------------------------------------------------
92	%macro eREPNC 0-1.nolist
93	db 64h
94	%ifnempty %1
95	%1
96	%endif
97	%endmacro
98
99
100	;--------------------------------------------------------------------
101	; The CLR1 instruction available on NEC V20/V30 CPUs.
102	;
103	; Clears bit indexed by Source in Destination.
104	;
105	; eCLR1
106	; Parameters:
107	; %1: Destination (register or memory location)
108	; %2: Source (CL or immediate value)
109	; Returns:
110	; Nothing
111	; Corrupts registers:
112	; Nothing (not even FLAGS)
113	;--------------------------------------------------------------------
114	%macro eCLR1 2.nolist
115	%assign w 0
116	%assign i 0
117	%ifnidni %2, cl
118	%assign i (1 << 3)
119	%endif
120	FSIS ], %1
121	%if strpos
122	FSIS BYTE, %1
123	%ifn strpos = 1
124	FSIS WORD, %1
125	%if strpos = 1
126	%assign w 1
127	%elif i
128	%if %2 > 7
129	%assign w 1
130	%endif
131	%else
132	%error "Memory operand needs a size specifier!"
133	%endif
134	%endif
135	%assign m (00b << 6)
136	FSIS [bx+si], %1
137	%if strpos
138	%assign rm 000b
139	%else
140	FSIS [bx+di], %1
141	%if strpos
142	%assign rm 001b
143	%else
144	FSIS [bp+si], %1
145	%if strpos
146	%assign rm 010b
147	%else
148	FSIS [bp+di], %1
149	%if strpos
150	%assign rm 011b
151	%else
152	FSIS [si], %1
153	%if strpos
154	%assign rm 100b
155	%else
156	FSIS [di], %1
157	%if strpos
158	%assign rm 101b
159	%else
160	FSIS [bx], %1
161	%if strpos
162	%assign rm 111b
163	%else
164	%error "Memory operands are not (yet) fully supported by the eCLR1 macro!"
165	%endif
166	%endif
167	%endif
168	%endif
169	%endif
170	%endif
171	%endif
172	%else
173	%assign m (11b << 6)
174	%ifidni %1, ax
175	%assign w 1
176	%assign rm regAX
177	%elifidni %1, bx
178	%assign w 1
179	%assign rm regBX
180	%elifidni %1, cx
181	%assign w 1
182	%assign rm regCX
183	%elifidni %1, dx
184	%assign w 1
185	%assign rm regDX
186	%elifidni %1, bp
187	%assign w 1
188	%assign rm regBP
189	%elifidni %1, sp
190	%assign w 1
191	%assign rm regSP
192	%elifidni %1, si
193	%assign w 1
194	%assign rm regSI
195	%elifidni %1, di
196	%assign w 1
197	%assign rm regDI
198	%elifidni %1, al
199	%assign rm regAL
200	%elifidni %1, ah
201	%assign rm regAH
202	%elifidni %1, bl
203	%assign rm regBL
204	%elifidni %1, bh
205	%assign rm regBH
206	%elifidni %1, cl
207	%assign rm regCL
208	%elifidni %1, ch
209	%assign rm regCH
210	%elifidni %1, dl
211	%assign rm regDL
212	%elifidni %1, dh
213	%assign rm regDH
214	%else
215	%error Invalid parameter passed to eCLR1! (%1)
216	%endif
217	%endif
218	db 0Fh, 12h \| i \| w, m \| rm
219	%if i
220	db %2
221	%if w
222	%if %2 > 15
223	%warning Possibly invalid parameter passed to eCLR1! (%2 > 15)
224	%endif
225	%else
226	%if %2 > 7
227	%warning Possibly invalid parameter passed to eCLR1! (%2 > 7)
228	%endif
229	%endif
230	%endif
231	%endmacro
232
233
234	;--------------------------------------------------------------------
235	; The SET1 instruction available on NEC V20/V30 CPUs.
236	;
237	; Sets bit indexed by Source in Destination.
238	;
239	; eSET1
240	; Parameters:
241	; %1: Destination (register or memory location)
242	; %2: Source (CL or immediate value)
243	; Returns:
244	; Nothing
245	; Corrupts registers:
246	; Nothing (not even FLAGS)
247	;--------------------------------------------------------------------
248	%macro eSET1 2.nolist
249	%assign w 0
250	%assign i 0
251	%ifnidni %2, cl
252	%assign i (1 << 3)
253	%endif
254	FSIS ], %1
255	%if strpos
256	FSIS BYTE, %1
257	%ifn strpos = 1
258	FSIS WORD, %1
259	%if strpos = 1
260	%assign w 1
261	%elif i
262	%if %2 > 7
263	%assign w 1
264	%endif
265	%else
266	%error "Memory operand needs a size specifier!"
267	%endif
268	%endif
269	%assign m (00b << 6)
270	FSIS [bx+si], %1
271	%if strpos
272	%assign rm 000b
273	%else
274	FSIS [bx+di], %1
275	%if strpos
276	%assign rm 001b
277	%else
278	FSIS [bp+si], %1
279	%if strpos
280	%assign rm 010b
281	%else
282	FSIS [bp+di], %1
283	%if strpos
284	%assign rm 011b
285	%else
286	FSIS [si], %1
287	%if strpos
288	%assign rm 100b
289	%else
290	FSIS [di], %1
291	%if strpos
292	%assign rm 101b
293	%else
294	FSIS [bx], %1
295	%if strpos
296	%assign rm 111b
297	%else
298	%error "Memory operands are not (yet) fully supported by the eSET1 macro!"
299	%endif
300	%endif
301	%endif
302	%endif
303	%endif
304	%endif
305	%endif
306	%else
307	%assign m (11b << 6)
308	%ifidni %1, ax
309	%assign w 1
310	%assign rm regAX
311	%elifidni %1, bx
312	%assign w 1
313	%assign rm regBX
314	%elifidni %1, cx
315	%assign w 1
316	%assign rm regCX
317	%elifidni %1, dx
318	%assign w 1
319	%assign rm regDX
320	%elifidni %1, bp
321	%assign w 1
322	%assign rm regBP
323	%elifidni %1, sp
324	%assign w 1
325	%assign rm regSP
326	%elifidni %1, si
327	%assign w 1
328	%assign rm regSI
329	%elifidni %1, di
330	%assign w 1
331	%assign rm regDI
332	%elifidni %1, al
333	%assign rm regAL
334	%elifidni %1, ah
335	%assign rm regAH
336	%elifidni %1, bl
337	%assign rm regBL
338	%elifidni %1, bh
339	%assign rm regBH
340	%elifidni %1, cl
341	%assign rm regCL
342	%elifidni %1, ch
343	%assign rm regCH
344	%elifidni %1, dl
345	%assign rm regDL
346	%elifidni %1, dh
347	%assign rm regDH
348	%else
349	%error Invalid parameter passed to eSET1! (%1)
350	%endif
351	%endif
352	db 0Fh, 14h \| i \| w, m \| rm
353	%if i
354	db %2
355	%if w
356	%if %2 > 15
357	%warning Possibly invalid parameter passed to eSET1! (%2 > 15)
358	%endif
359	%else
360	%if %2 > 7
361	%warning Possibly invalid parameter passed to eSET1! (%2 > 7)
362	%endif
363	%endif
364	%endif
365	%endmacro
366
367
368	;--------------------------------------------------------------------
369	; The NOT1 instruction available on NEC V20/V30 CPUs.
370	;
371	; Inverts bit indexed by Source in Destination.
372	;
373	; eNOT1
374	; Parameters:
375	; %1: Destination (register or memory location)
376	; %2: Source (CL or immediate value)
377	; Returns:
378	; Nothing
379	; Corrupts registers:
380	; Nothing (not even FLAGS)
381	;--------------------------------------------------------------------
382	%macro eNOT1 2.nolist
383	%assign w 0
384	%assign i 0
385	%ifnidni %2, cl
386	%assign i (1 << 3)
387	%endif
388	FSIS ], %1
389	%if strpos
390	FSIS BYTE, %1
391	%ifn strpos = 1
392	FSIS WORD, %1
393	%if strpos = 1
394	%assign w 1
395	%elif i
396	%if %2 > 7
397	%assign w 1
398	%endif
399	%else
400	%error "Memory operand needs a size specifier!"
401	%endif
402	%endif
403	%assign m (00b << 6)
404	FSIS [bx+si], %1
405	%if strpos
406	%assign rm 000b
407	%else
408	FSIS [bx+di], %1
409	%if strpos
410	%assign rm 001b
411	%else
412	FSIS [bp+si], %1
413	%if strpos
414	%assign rm 010b
415	%else
416	FSIS [bp+di], %1
417	%if strpos
418	%assign rm 011b
419	%else
420	FSIS [si], %1
421	%if strpos
422	%assign rm 100b
423	%else
424	FSIS [di], %1
425	%if strpos
426	%assign rm 101b
427	%else
428	FSIS [bx], %1
429	%if strpos
430	%assign rm 111b
431	%else
432	%error "Memory operands are not (yet) fully supported by the eNOT1 macro!"
433	%endif
434	%endif
435	%endif
436	%endif
437	%endif
438	%endif
439	%endif
440	%else
441	%assign m (11b << 6)
442	%ifidni %1, ax
443	%assign w 1
444	%assign rm regAX
445	%elifidni %1, bx
446	%assign w 1
447	%assign rm regBX
448	%elifidni %1, cx
449	%assign w 1
450	%assign rm regCX
451	%elifidni %1, dx
452	%assign w 1
453	%assign rm regDX
454	%elifidni %1, bp
455	%assign w 1
456	%assign rm regBP
457	%elifidni %1, sp
458	%assign w 1
459	%assign rm regSP
460	%elifidni %1, si
461	%assign w 1
462	%assign rm regSI
463	%elifidni %1, di
464	%assign w 1
465	%assign rm regDI
466	%elifidni %1, al
467	%assign rm regAL
468	%elifidni %1, ah
469	%assign rm regAH
470	%elifidni %1, bl
471	%assign rm regBL
472	%elifidni %1, bh
473	%assign rm regBH
474	%elifidni %1, cl
475	%assign rm regCL
476	%elifidni %1, ch
477	%assign rm regCH
478	%elifidni %1, dl
479	%assign rm regDL
480	%elifidni %1, dh
481	%assign rm regDH
482	%else
483	%error Invalid parameter passed to eNOT1! (%1)
484	%endif
485	%endif
486	db 0Fh, 16h \| i \| w, m \| rm
487	%if i
488	db %2
489	%if w
490	%if %2 > 15
491	%warning Possibly invalid parameter passed to eNOT1! (%2 > 15)
492	%endif
493	%else
494	%if %2 > 7
495	%warning Possibly invalid parameter passed to eNOT1! (%2 > 7)
496	%endif
497	%endif
498	%endif
499	%endmacro
500
501
502	;--------------------------------------------------------------------
503	; The TEST1 instruction available on NEC V20/V30 CPUs.
504	;
505	; Tests bit indexed by Source in Destination.
506	;
507	; eTEST1
508	; Parameters:
509	; %1: Destination (register or memory location)
510	; %2: Source (CL or immediate value)
511	; Returns:
512	; ZF: Set if tested bit is zero
513	; Cleared if tested bit is not zero
514	; CF: Cleared
515	; OF: Cleared
516	; Corrupts registers:
517	; All other FLAGS
518	;--------------------------------------------------------------------
519	%macro eTEST1 2.nolist
520	%assign w 0
521	%assign i 0
522	%ifnidni %2, cl
523	%assign i (1 << 3)
524	%endif
525	FSIS ], %1
526	%if strpos
527	FSIS BYTE, %1
528	%ifn strpos = 1
529	FSIS WORD, %1
530	%if strpos = 1
531	%assign w 1
532	%elif i
533	%if %2 > 7
534	%assign w 1
535	%endif
536	%else
537	%error "Memory operand needs a size specifier!"
538	%endif
539	%endif
540	%assign m (00b << 6)
541	FSIS [bx+si], %1
542	%if strpos
543	%assign rm 000b
544	%else
545	FSIS [bx+di], %1
546	%if strpos
547	%assign rm 001b
548	%else
549	FSIS [bp+si], %1
550	%if strpos
551	%assign rm 010b
552	%else
553	FSIS [bp+di], %1
554	%if strpos
555	%assign rm 011b
556	%else
557	FSIS [si], %1
558	%if strpos
559	%assign rm 100b
560	%else
561	FSIS [di], %1
562	%if strpos
563	%assign rm 101b
564	%else
565	FSIS [bx], %1
566	%if strpos
567	%assign rm 111b
568	%else
569	%error "Memory operands are not (yet) fully supported by the eTEST1 macro!"
570	%endif
571	%endif
572	%endif
573	%endif
574	%endif
575	%endif
576	%endif
577	%else
578	%assign m (11b << 6)
579	%ifidni %1, ax
580	%assign w 1
581	%assign rm regAX
582	%elifidni %1, bx
583	%assign w 1
584	%assign rm regBX
585	%elifidni %1, cx
586	%assign w 1
587	%assign rm regCX
588	%elifidni %1, dx
589	%assign w 1
590	%assign rm regDX
591	%elifidni %1, bp
592	%assign w 1
593	%assign rm regBP
594	%elifidni %1, sp
595	%assign w 1
596	%assign rm regSP
597	%elifidni %1, si
598	%assign w 1
599	%assign rm regSI
600	%elifidni %1, di
601	%assign w 1
602	%assign rm regDI
603	%elifidni %1, al
604	%assign rm regAL
605	%elifidni %1, ah
606	%assign rm regAH
607	%elifidni %1, bl
608	%assign rm regBL
609	%elifidni %1, bh
610	%assign rm regBH
611	%elifidni %1, cl
612	%assign rm regCL
613	%elifidni %1, ch
614	%assign rm regCH
615	%elifidni %1, dl
616	%assign rm regDL
617	%elifidni %1, dh
618	%assign rm regDH
619	%else
620	%error Invalid parameter passed to eTEST1! (%1)
621	%endif
622	%endif
623	db 0Fh, 10h \| i \| w, m \| rm
624	%if i
625	db %2
626	%if w
627	%if %2 > 15
628	%warning Possibly invalid parameter passed to eTEST1! (%2 > 15)
629	%endif
630	%else
631	%if %2 > 7
632	%warning Possibly invalid parameter passed to eTEST1! (%2 > 7)
633	%endif
634	%endif
635	%endif
636	%endmacro
637
638
639	;--------------------------------------------------------------------
640	; The EXT instruction available on NEC V20/V30 CPUs.
641	;
642	; Loads AX with a zero-extended bitfield, from [xS:SI] plus an additional
643	; bit offset specified in Destination, with Source+1 number of bits.
644	; Both Source and Destination must be at most 15.
645	;
646	; eEXT
647	; Parameters:
648	; xS:SI: Pointer to bitfield. Default segment is DS but can be overridden
649	; %1: Destination (8-bit register)
650	; %2: Source (8-bit register or immediate value)
651	; Returns:
652	; AX: Extracted bitfield
653	; %1: (%1 + %2 + 1) MOD 16
654	; SI: SI + 2 (but only if %1 wrapped around)
655	; Corrupts registers:
656	; FLAGS
657	;--------------------------------------------------------------------
658	%macro eEXT 2.nolist
659	%assign m (11b << 6)
660	%assign i 0
661	%assign r 0
662	%ifidni %2, al
663	%assign r (regAL << 3)
664	%elifidni %2, ah
665	%assign r (regAH << 3)
666	%elifidni %2, bl
667	%assign r (regBL << 3)
668	%elifidni %2, bh
669	%assign r (regBH << 3)
670	%elifidni %2, cl
671	%assign r (regCL << 3)
672	%elifidni %2, ch
673	%assign r (regCH << 3)
674	%elifidni %2, dl
675	%assign r (regDL << 3)
676	%elifidni %2, dh
677	%assign r (regDH << 3)
678	%else
679	%if %2 > 15
680	%error Invalid parameter passed to eEXT! (%2 > 15)
681	%endif
682	%assign i (1 << 3)
683	%endif
684	%ifidni %1, al
685	%assign rm regAL
686	%elifidni %1, ah
687	%assign rm regAH
688	%elifidni %1, bl
689	%assign rm regBL
690	%elifidni %1, bh
691	%assign rm regBH
692	%elifidni %1, cl
693	%assign rm regCL
694	%elifidni %1, ch
695	%assign rm regCH
696	%elifidni %1, dl
697	%assign rm regDL
698	%elifidni %1, dh
699	%assign rm regDH
700	%else
701	%error Invalid parameter passed to eEXT! (%1)
702	%endif
703	db 0Fh, 33h \| i, m \| r \| rm
704	%if i
705	db %2
706	%endif
707	%endmacro
708
709
710	;--------------------------------------------------------------------
711	; The INS instruction available on NEC V20/V30 CPUs.
712	;
713	; Stores the Source+1 least significant bits in AX to [xS:DI]
714	; plus an additional bit offset specified in Destination.
715	; Both Source and Destination must be at most 15.
716	;
717	; eINS
718	; Parameters:
719	; xS:DI: Pointer to bitfield. Default segment is ES but can be overridden
720	; %1: Destination (8-bit register)
721	; %2: Source (8-bit register or immediate value)
722	; Returns:
723	; %1: (%1 + %2 + 1) MOD 16
724	; DI: DI + 2 (but only if %1 wrapped around)
725	; Corrupts registers:
726	; FLAGS
727	;--------------------------------------------------------------------
728	%macro eINS 2.nolist
729	%assign m (11b << 6)
730	%assign i 0
731	%assign r 0
732	%ifidni %2, al
733	%assign r (regAL << 3)
734	%elifidni %2, ah
735	%assign r (regAH << 3)
736	%elifidni %2, bl
737	%assign r (regBL << 3)
738	%elifidni %2, bh
739	%assign r (regBH << 3)
740	%elifidni %2, cl
741	%assign r (regCL << 3)
742	%elifidni %2, ch
743	%assign r (regCH << 3)
744	%elifidni %2, dl
745	%assign r (regDL << 3)
746	%elifidni %2, dh
747	%assign r (regDH << 3)
748	%else
749	%if %2 > 15
750	%error Invalid parameter passed to eINS! (%2 > 15)
751	%endif
752	%assign i (1 << 3)
753	%endif
754	%ifidni %1, al
755	%assign rm regAL
756	%elifidni %1, ah
757	%assign rm regAH
758	%elifidni %1, bl
759	%assign rm regBL
760	%elifidni %1, bh
761	%assign rm regBH
762	%elifidni %1, cl
763	%assign rm regCL
764	%elifidni %1, ch
765	%assign rm regCH
766	%elifidni %1, dl
767	%assign rm regDL
768	%elifidni %1, dh
769	%assign rm regDH
770	%else
771	%error Invalid parameter passed to eINS! (%1)
772	%endif
773	db 0Fh, 31h \| i, m \| r \| rm
774	%if i
775	db %2
776	%endif
777	%endmacro
778
779
780	;--------------------------------------------------------------------
781	; The ROL4 instruction available on NEC V20/V30 CPUs.
782	;
783	; Rotates the destination four bits to the left via the low nibble of AL.
784	; If the destination is AL then the high and low nibbles will be swapped.
785	;
786	; eROL4
787	; Parameters:
788	; %1: 8-bit destination (register or memory location)
789	; Returns:
790	; AL: The low nibble of AL in the high nibble of AL
791	; The high nibble of %1 in the low nibble of AL
792	; %1: The low nibble of %1 in the high nibble of %1
793	; The low nibble of AL in the low nibble of %1
794	; Corrupts registers:
795	; Nothing (not even FLAGS)
796	;--------------------------------------------------------------------
797	%macro eROL4 1.nolist
798	FSIS ], %1
799	%if strpos
800	%assign m (00b << 6)
801	FSIS [bx+si], %1
802	%if strpos
803	%assign rm 000b
804	%else
805	FSIS [bx+di], %1
806	%if strpos
807	%assign rm 001b
808	%else
809	FSIS [bp+si], %1
810	%if strpos
811	%assign rm 010b
812	%else
813	FSIS [bp+di], %1
814	%if strpos
815	%assign rm 011b
816	%else
817	FSIS [si], %1
818	%if strpos
819	%assign rm 100b
820	%else
821	FSIS [di], %1
822	%if strpos
823	%assign rm 101b
824	%else
825	FSIS [bx], %1
826	%if strpos
827	%assign rm 111b
828	%else
829	%error "Memory operands are not (yet) fully supported by the eROL4 macro!"
830	%endif
831	%endif
832	%endif
833	%endif
834	%endif
835	%endif
836	%endif
837	%else
838	%assign m (11b << 6)
839	%ifidni %1, al
840	%assign rm regAL
841	%elifidni %1, ah
842	%assign rm regAH
843	%elifidni %1, bl
844	%assign rm regBL
845	%elifidni %1, bh
846	%assign rm regBH
847	%elifidni %1, cl
848	%assign rm regCL
849	%elifidni %1, ch
850	%assign rm regCH
851	%elifidni %1, dl
852	%assign rm regDL
853	%elifidni %1, dh
854	%assign rm regDH
855	%else
856	%error Invalid parameter passed to eROL4! (%1)
857	%endif
858	%endif
859	db 0Fh, 28h, m \| rm
860	%endmacro
861
862
863	;--------------------------------------------------------------------
864	; The ROR4 instruction available on NEC V20/V30 CPUs.
865	;
866	; Rotates the destination four bits to the right via the low nibble of AL.
867	; If the destination is AL then nothing changes.
868	;
869	; eROR4
870	; Parameters:
871	; %1: 8-bit destination (register or memory location)
872	; Returns:
873	; AL: The high nibble of %1 in the high nibble of AL
874	; The low nibble of %1 in the low nibble of AL
875	; %1: The high nibble of %1 in the low nibble of %1
876	; The low nibble of AL in the high nibble of %1
877	; Corrupts registers:
878	; Nothing (not even FLAGS)
879	;--------------------------------------------------------------------
880	%macro eROR4 1.nolist
881	FSIS ], %1
882	%if strpos
883	%assign m (00b << 6)
884	FSIS [bx+si], %1
885	%if strpos
886	%assign rm 000b
887	%else
888	FSIS [bx+di], %1
889	%if strpos
890	%assign rm 001b
891	%else
892	FSIS [bp+si], %1
893	%if strpos
894	%assign rm 010b
895	%else
896	FSIS [bp+di], %1
897	%if strpos
898	%assign rm 011b
899	%else
900	FSIS [si], %1
901	%if strpos
902	%assign rm 100b
903	%else
904	FSIS [di], %1
905	%if strpos
906	%assign rm 101b
907	%else
908	FSIS [bx], %1
909	%if strpos
910	%assign rm 111b
911	%else
912	%error "Memory operands are not (yet) fully supported by the eROR4 macro!"
913	%endif
914	%endif
915	%endif
916	%endif
917	%endif
918	%endif
919	%endif
920	%else
921	%assign m (11b << 6)
922	%ifidni %1, al
923	%assign rm regAL
924	%elifidni %1, ah
925	%assign rm regAH
926	%elifidni %1, bl
927	%assign rm regBL
928	%elifidni %1, bh
929	%assign rm regBH
930	%elifidni %1, cl
931	%assign rm regCL
932	%elifidni %1, ch
933	%assign rm regCH
934	%elifidni %1, dl
935	%assign rm regDL
936	%elifidni %1, dh
937	%assign rm regDH
938	%else
939	%error Invalid parameter passed to eROR4! (%1)
940	%endif
941	%endif
942	db 0Fh, 2Ah, m \| rm
943	%endmacro
944
945
946	;--------------------------------------------------------------------
947	; The ADD4S instruction available on NEC V20/V30 CPUs.
948	;
949	; Adds packed BCD string at xS:SI to packed BCD string at ES:DI
950	; with (preferably even) nibble count in CL.
951	;
952	; eADD4S
953	; Parameters:
954	; CL: Number of packed BCD digits (nibbles in string) ranging
955	; from 1 to 254. Should be an even number or the CPU will
956	; treat it as CL+1.
957	; xS:SI: Pointer to source string. Default segment is DS but
958	; can be overridden.
959	; ES:DI: Pointer to destination string.
960	; Returns:
961	; ES:DI: Pointer to destination string.
962	; CF/ZF: Set according to result.
963	; Corrupts registers:
964	; All other FLAGS
965	;--------------------------------------------------------------------
966	%macro eADD4S 0.nolist
967	db 0Fh, 20h
968	%endmacro
969
970
971	;--------------------------------------------------------------------
972	; The SUB4S instruction available on NEC V20/V30 CPUs.
973	;
974	; Subtracts packed BCD string at xS:SI from packed BCD string at ES:DI
975	; with (preferably even) nibble count in CL.
976	;
977	; eSUB4S
978	; Parameters:
979	; CL: Number of packed BCD digits (nibbles in string) ranging
980	; from 1 to 254. Should be an even number or the CPU will
981	; treat it as CL+1.
982	; xS:SI: Pointer to source string. Default segment is DS but
983	; can be overridden.
984	; ES:DI: Pointer to destination string.
985	; Returns:
986	; ES:DI: Pointer to destination string.
987	; CF/ZF: Set according to result.
988	; Corrupts registers:
989	; All other FLAGS
990	;--------------------------------------------------------------------
991	%macro eSUB4S 0.nolist
992	db 0Fh, 22h
993	%endmacro
994
995
996	;--------------------------------------------------------------------
997	; The CMP4S instruction available on NEC V20/V30 CPUs.
998	;
999	; Compares packed BCD string at xS:SI with packed BCD string at ES:DI
1000	; with (preferably even) nibble count in CL.
1001	;
1002	; eCMP4S
1003	; Parameters:
1004	; CL: Number of packed BCD digits (nibbles in string) ranging
1005	; from 1 to 254. Should be an even number or the CPU will
1006	; treat it as CL+1.
1007	; xS:SI: Pointer to source string. Default segment is DS but
1008	; can be overridden.
1009	; ES:DI: Pointer to destination string.
1010	; Returns:
1011	; CF/ZF: Set according to result.
1012	; Corrupts registers:
1013	; All other FLAGS
1014	;--------------------------------------------------------------------
1015	%macro eCMP4S 0.nolist
1016	db 0Fh, 26h
1017	%endmacro
1018
1019
1020	;--------------------------------------------------------------------
1021	; The BRKEM instruction available on NEC V20/V30 CPUs.
1022	;
1023	; Starts 8080 CPU emulation mode by invoking the software interrupt in %1.
1024	;
1025	; eBRKEM
1026	; Parameters:
1027	; %1: 8-bit interrupt vector number
1028	; Returns:
1029	; Nothing
1030	; Corrupts registers:
1031	; Nothing
1032	;--------------------------------------------------------------------
1033	%macro eBRKEM 1.nolist
1034	%if %1 > 255
1035	%error Invalid parameter passed to eBRKEM! (%1 > 255)
1036	%else
1037	db 0Fh, 0FFh, %1
1038	%endif
1039	%endmacro
1040
1041
1042	;--------------------------------------------------------------------
1043	; The CALLN instruction available on NEC V20/V30 CPUs.
1044	;
1045	; This instruction is used while in 8080 CPU emulation mode to invoke
1046	; the native (x86) software interrupt in %1.
1047	;
1048	; eCALLN
1049	; Parameters:
1050	; %1: 8-bit interrupt vector number
1051	; Returns:
1052	; Nothing
1053	; Corrupts registers:
1054	; Nothing
1055	;--------------------------------------------------------------------
1056	%macro eCALLN 1.nolist
1057	%if %1 > 255
1058	%error Invalid parameter passed to eCALLN! (%1 > 255)
1059	%else
1060	db 0EDh, 0EDh, %1
1061	%endif
1062	%endmacro
1063
1064
1065	;--------------------------------------------------------------------
1066	; The RETEM instruction available on NEC V20/V30 CPUs.
1067	;
1068	; Ends 8080 CPU emulation mode by returning from the software interrupt
1069	; invoked by BRKEM.
1070	;
1071	; eRETEM
1072	; Parameters:
1073	; Nothing
1074	; Returns:
1075	; Nothing
1076	; Corrupts registers:
1077	; Nothing
1078	;--------------------------------------------------------------------
1079	%macro eRETEM 0.nolist
1080	db 0EDh, 0FDh
1081	%endmacro
1082
1083
1084	%endif ; NEC_V_INC
1085

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