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Last change
on this file since 590 was 568, checked in by krille_n_@…, 10 years ago |
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Changes:
- SerDrive: Using named pipe mode (serdrive -p) now works under Windows XP/2000/Server 2003.
- checksum.pl: Added a compatibility fix for 3Com 3C503 cards.
- XTIDECFG will now scan every possible segment address to find and load the BIOS and/or its settings from EEPROM. This should simplify things for people using combined option ROMs.
- Fixed a bug from r521 in BootSector.asm where the BIOS would not display a timeout error if it failed to load the boot sector from harddrive.
- Fixed a bug from r541 in CompatibleDPT.asm where CompatibleDPT_CreateDeviceParameterTableExtensionToESBXfromDPTinDSSI would generate an invalid checksum in the DPTE.
- Optimizations and other fixes.
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File size:
1.7 KB
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| [247] | 1 | ; Project name : Assembly Library
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| 2 | ; Description : Delay macros.
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| 3 | %ifndef DELAY_INC
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| 4 | %define DELAY_INC
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| 5 |
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| 6 | ;--------------------------------------------------------------------
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| [568] | 7 | ; Clears prefetch queue by jumping to the next instruction.
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| 8 | ; This delays much more than the nop instruction on fast systems.
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| [247] | 9 | ;
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| 10 | ; JMP_DELAY
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| 11 | ; Parameters
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| 12 | ; Nothing
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| 13 | ; Returns:
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| 14 | ; Nothing
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| 15 | ; Corrupts registers:
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| 16 | ; Nothing
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| 17 | ;--------------------------------------------------------------------
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| 18 | %macro JMP_DELAY 0
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| 19 | jmp SHORT %%NextInstruction
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| 20 | %%NextInstruction:
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| 21 | %endmacro
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| 22 |
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| 23 |
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| 24 | ;--------------------------------------------------------------------
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| 25 | ; Mimimun delays (without fetching) with some CPU architectures:
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| 26 | ; 8088/8086: 17 cycles for jump + 5 cycles for last comparison
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| 27 | ; 286: 10 cycles for jump + 4 cycles for last comparison
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| 28 | ; 386: 13 cycles for jump + ? cycles for last comparison
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| 29 | ; 486: 7 cycles for jump + 6 cycles for last comparison
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| 30 | ;
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| [287] | 31 | ; LOOP instruction uses two bytes so aligned fetching will require:
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| [567] | 32 | ; 8088: 8 cycles (two BYTE reads)
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| 33 | ; 8086: 4 cycles (one WORD read)
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| 34 | ; 286: 2 cycles + wait states (usually 1)
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| 35 | ; 386: ?
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| [287] | 36 | ; 486: Fetched only once to internal cache
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| 37 | ;
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| 38 | ; DELAY_WITH_LOOP_INSTRUCTION_NA ; No JUMP_ALIGN
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| [247] | 39 | ; DELAY_WITH_LOOP_INSTRUCTION
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| 40 | ; Parameters
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| 41 | ; CX: Loop iterations (0 is maximum delay with 65536 iterations)
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| 42 | ; Returns:
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| [287] | 43 | ; CX: Zero
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| 44 | ; Corrupts registers:
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| [247] | 45 | ; Nothing
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| 46 | ;--------------------------------------------------------------------
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| [287] | 47 | %macro DELAY_WITH_LOOP_INSTRUCTION_NA 0
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| 48 | %%StartOfLoop:
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| 49 | loop %%StartOfLoop
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| 50 | %endmacro
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| 51 |
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| [247] | 52 | %macro DELAY_WITH_LOOP_INSTRUCTION 0
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| [287] | 53 | ALIGN JUMP_ALIGN
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| [247] | 54 | %%StartOfLoop:
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| 55 | loop %%StartOfLoop
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| 56 | %endmacro
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| 57 |
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| 58 |
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| 59 | %endif ; DELAY_INC
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