1 | ; Project name : XTIDE Universal BIOS |
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2 | ; Description : Equates for 8237 DMA Controllers. |
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3 | |
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4 | ; |
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5 | ; XTIDE Universal BIOS and Associated Tools |
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6 | ; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2012 by XTIDE Universal BIOS Team. |
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7 | ; |
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8 | ; This program is free software; you can redistribute it and/or modify |
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9 | ; it under the terms of the GNU General Public License as published by |
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10 | ; the Free Software Foundation; either version 2 of the License, or |
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11 | ; (at your option) any later version. |
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12 | ; |
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13 | ; This program is distributed in the hope that it will be useful, |
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14 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of |
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15 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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16 | ; GNU General Public License for more details. |
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17 | ; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html |
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18 | ; |
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19 | |
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20 | %ifndef DMA_CONTROLLER_INC |
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21 | %define DMA_CONTROLLER_INC |
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22 | |
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23 | ; 8237 Master (8-bit) and Slave (16-bit) DMA Controller Ports |
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24 | |
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25 | ; Page Registers |
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26 | PAGE_DMA8_CH_1 EQU 83h |
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27 | PAGE_DMA8_CH_2 EQU 81h |
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28 | PAGE_DMA8_CH_3 EQU 82h |
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29 | PAGE_DMA16_CH_5 EQU 8Bh ; AT+ |
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30 | PAGE_DMA16_CH_6 EQU 89h ; AT+ |
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31 | PAGE_DMA16_CH_7 EQU 8Ah ; AT+ |
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32 | |
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33 | ; Base and Current Address Registers |
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34 | BASE_AND_CURRENT_ADDRESS_REGISTER_DMA8_CH1_out EQU 02h |
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35 | BASE_AND_CURRENT_ADDRESS_REGISTER_DMA8_CH2_out EQU 04h |
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36 | BASE_AND_CURRENT_ADDRESS_REGISTER_DMA8_CH3_out EQU 06h |
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37 | BASE_AND_CURRENT_ADDRESS_REGISTER_DMA16_CH5_out EQU 0C4h ; AT+ |
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38 | BASE_AND_CURRENT_ADDRESS_REGISTER_DMA16_CH6_out EQU 0C8h ; AT+ |
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39 | BASE_AND_CURRENT_ADDRESS_REGISTER_DMA16_CH7_out EQU 0CCh ; AT+ |
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40 | CURRENT_ADDRESS_REGISTER_DMA8_CH1_in EQU 02h |
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41 | CURRENT_ADDRESS_REGISTER_DMA8_CH2_in EQU 04h |
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42 | CURRENT_ADDRESS_REGISTER_DMA8_CH3_in EQU 06h |
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43 | CURRENT_ADDRESS_REGISTER_DMA16_CH5_in EQU 0C4h ; AT+ |
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44 | CURRENT_ADDRESS_REGISTER_DMA16_CH6_in EQU 0C8h ; AT+ |
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45 | CURRENT_ADDRESS_REGISTER_DMA16_CH7_in EQU 0CCh ; AT+ |
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46 | |
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47 | ; Base and Current Count Registers |
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48 | BASE_AND_CURRENT_COUNT_REGISTER_DMA8_CH1_out EQU 03h |
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49 | BASE_AND_CURRENT_COUNT_REGISTER_DMA8_CH2_out EQU 05h |
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50 | BASE_AND_CURRENT_COUNT_REGISTER_DMA8_CH3_out EQU 07h |
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51 | BASE_AND_CURRENT_COUNT_REGISTER_DMA16_CH5_out EQU 0C6h ; AT+ |
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52 | BASE_AND_CURRENT_COUNT_REGISTER_DMA16_CH6_out EQU 0CAh ; AT+ |
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53 | BASE_AND_CURRENT_COUNT_REGISTER_DMA16_CH7_out EQU 0CEh ; AT+ |
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54 | CURRENT_COUNT_REGISTER_DMA8_CH1_in EQU 03h |
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55 | CURRENT_COUNT_REGISTER_DMA8_CH2_in EQU 05h |
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56 | CURRENT_COUNT_REGISTER_DMA8_CH3_in EQU 07h |
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57 | CURRENT_COUNT_REGISTER_DMA16_CH5_in EQU 0C6h ; AT+ |
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58 | CURRENT_COUNT_REGISTER_DMA16_CH6_in EQU 0CAh ; AT+ |
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59 | CURRENT_COUNT_REGISTER_DMA16_CH7_in EQU 0CEh ; AT+ |
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60 | |
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61 | ; Command Registers (Command Value used by PCs is 0) |
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62 | COMMAND_REGISTER_DMA8_out EQU 08h |
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63 | COMMAND_REGISTER_DMA16_out EQU 0D0h ; AT+ |
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64 | MEM_TO_MEM_XFERS_DISABLE EQU 0 |
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65 | MEM_TO_MEM_XFERS_ENABLE EQU (1<<0) |
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66 | |
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67 | CH0_ADDRESS_HOLD_DISABLE EQU 0 |
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68 | CH0_ADDRESS_HOLD_ENABLE EQU (1<<1) ; When MEM_TO_MEM_XFERS_ENABLE |
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69 | |
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70 | CONTROLLER_ENABLE EQU 0 |
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71 | CONTROLLER_DISABLE EQU (1<<2) ; Instead of Controller Enable |
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72 | |
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73 | NORMAL_TIMING EQU 0 |
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74 | COMPRESSED_TIMING EQU (1<<3) ; Instead of Normal Timing when MEM_TO_MEM_XFERS_DISABLE |
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75 | |
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76 | FIXED_PRIORITY EQU 0 |
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77 | ROTATING_PRIORITY EQU (1<<4) ; Instead of Fixed Priority |
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78 | |
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79 | LATE_WRITE_SELECTION EQU 0 |
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80 | EXTENDED_WRITE_SELECTION EQU (1<<5) ; Instead of Late Write Selection |
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81 | |
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82 | DREQ_SENSE_ACTIVE_HIGH EQU 0 |
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83 | DREQ_SENSE_ACTIVE_LOW EQU (1<<6) ; Instead of DREQ Sense Active High |
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84 | |
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85 | DACK_SENSE_ACTIVE_LOW EQU 0 |
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86 | DACK_SENSE_ACTIVE_HIGH EQU (1<<7) ; Instead of DACK Sense Active Low |
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87 | |
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88 | |
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89 | ; Status Registers (reading will clear Terminal Count flags) |
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90 | STATUS_REGISTER_DMA8_in EQU COMMAND_REGISTER_DMA8_out |
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91 | FLG_CH1_HAS_REACHED_TERMINAL_COUNT EQU (1<<1) |
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92 | FLG_CH2_HAS_REACHED_TERMINAL_COUNT EQU (1<<2) |
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93 | FLG_CH3_HAS_REACHED_TERMINAL_COUNT EQU (1<<3) |
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94 | FLG_CH1_REQUEST EQU (1<<5) |
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95 | FLG_CH2_REQUEST EQU (1<<6) |
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96 | FLG_CH3_REQUEST EQU (1<<7) |
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97 | STATUS_REGISTER_DMA16_in EQU COMMAND_REGISTER_DMA16_out ; AT+ |
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98 | FLG_CH5_HAS_REACHED_TERMINAL_COUNT EQU (1<<1) |
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99 | FLG_CH6_HAS_REACHED_TERMINAL_COUNT EQU (1<<2) |
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100 | FLG_CH7_HAS_REACHED_TERMINAL_COUNT EQU (1<<3) |
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101 | FLG_CH5_REQUEST EQU (1<<5) |
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102 | FLG_CH6_REQUEST EQU (1<<6) |
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103 | FLG_CH7_REQUEST EQU (1<<7) |
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104 | |
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105 | |
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106 | ; Request Registers (Software DMA Request) |
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107 | REQUEST_REGISTER_DMA8_out EQU 09h |
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108 | FLG_SET_REQUEST EQU (1<<2) |
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109 | CLEAR_CH1_REQUEST EQU CHANNEL_1 |
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110 | CLEAR_CH2_REQUEST EQU CHANNEL_2 |
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111 | CLEAR_CH3_REQUEST EQU CHANNEL_3 |
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112 | SET_CH1_REQUEST EQU (CHANNEL_1 | FLG_SET_REQUEST) |
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113 | SET_CH2_REQUEST EQU (CHANNEL_2 | FLG_SET_REQUEST) |
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114 | SET_CH3_REQUEST EQU (CHANNEL_3 | FLG_SET_REQUEST) |
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115 | REQUEST_REGISTER_DMA16_out EQU 0D2h ; AT+ |
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116 | CLEAR_CH5_REQUEST EQU CLEAR_CH1_REQUEST |
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117 | CLEAR_CH6_REQUEST EQU CLEAR_CH2_REQUEST |
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118 | CLEAR_CH7_REQUEST EQU CLEAR_CH3_REQUEST |
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119 | SET_CH5_REQUEST EQU SET_CH1_REQUEST |
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120 | SET_CH6_REQUEST EQU SET_CH2_REQUEST |
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121 | SET_CH7_REQUEST EQU SET_CH3_REQUEST |
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122 | |
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123 | |
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124 | ; Mask Registers (setting a mask bit disables DMA channel) |
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125 | MASK_REGISTER_DMA8_out EQU 0Ah |
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126 | FLG_SET_MASK EQU FLG_SET_REQUEST |
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127 | CLEAR_CH1_MASK_BIT EQU CLEAR_CH1_REQUEST |
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128 | CLEAR_CH2_MASK_BIT EQU CLEAR_CH2_REQUEST |
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129 | CLEAR_CH3_MASK_BIT EQU CLEAR_CH3_REQUEST |
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130 | SET_CH1_MASK_BIT EQU SET_CH1_REQUEST |
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131 | SET_CH2_MASK_BIT EQU SET_CH2_REQUEST |
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132 | SET_CH3_MASK_BIT EQU SET_CH3_REQUEST |
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133 | MASK_REGISTER_DMA16_out EQU 0D4h ; AT+ |
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134 | CLEAR_CH5_MASK_BIT EQU CLEAR_CH5_REQUEST |
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135 | CLEAR_CH6_MASK_BIT EQU CLEAR_CH6_REQUEST |
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136 | CLEAR_CH7_MASK_BIT EQU CLEAR_CH7_REQUEST |
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137 | SET_CH5_MASK_BIT EQU SET_CH5_REQUEST |
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138 | SET_CH6_MASK_BIT EQU SET_CH6_REQUEST |
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139 | SET_CH7_MASK_BIT EQU SET_CH7_REQUEST |
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140 | |
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141 | |
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142 | ; Mode Registers |
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143 | MODE_REGISTER_DMA8_out EQU 0Bh |
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144 | ; Select channel number (bits 0...1) |
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145 | CHANNEL_1 EQU 1 |
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146 | CHANNEL_2 EQU 2 |
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147 | CHANNEL_3 EQU 3 |
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148 | MODE_REGISTER_DMA16_out EQU 0D6h ; AT+ |
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149 | CHANNEL_5 EQU CHANNEL_1 |
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150 | CHANNEL_6 EQU CHANNEL_2 |
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151 | CHANNEL_7 EQU CHANNEL_3 |
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152 | ; Transfer type (bits 2...3) |
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153 | VERIFY EQU (0<<2) |
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154 | WRITE EQU (1<<2) ; To memory |
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155 | READ EQU (2<<2) ; From memory |
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156 | ; Autoinitialization enable/disable (bit 4) |
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157 | AUTOINIT_DISABLE EQU 0 |
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158 | AUTOINIT_ENABLE EQU (1<<4) ; Instead of autoinitialization disable |
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159 | ; Address increment/decrement select (bit 5) |
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160 | ADDRESS_INCREMENT EQU 0 |
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161 | ADDRESS_DECREMENT EQU (1<<5) ; Instead of address increment |
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162 | ; Mode type selection (bits 6...7) |
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163 | DEMAND_MODE EQU (0<<6) |
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164 | SINGLE_MODE EQU (1<<6) |
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165 | BLOCK_MODE EQU (2<<6) |
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166 | CASCADE_MODE EQU (3<<6) |
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167 | |
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168 | |
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169 | ; Clear Byte Flip-Flops (any byte resets low/high byte flip-flop to low) |
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170 | CLEAR_FLIPFLOP_DMA8_out EQU 0Ch |
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171 | CLEAR_FLIPFLOP_DMA16_out EQU 0D8h ; AT+ |
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172 | |
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173 | |
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174 | ; Temporary Registers |
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175 | TEMP_REGISTER_DMA8_in EQU 0Dh |
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176 | TEMP_REGISTER_DMA16_in EQU 0DAh ; AT+ |
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177 | |
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178 | |
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179 | ; Master Clear (any byte does the same as hardware reset) |
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180 | MASTER_CLEAR_DMA8_out EQU TEMP_REGISTER_DMA8_in |
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181 | MASTER_CLEAR_DMA16_out EQU TEMP_REGISTER_DMA16_in ; AT+ |
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182 | |
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183 | |
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184 | ; Clear all mask bits (any byte enables all DMA channels) |
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185 | CLEAR_ALL_MASK_BITS_DMA8_out EQU 0Eh |
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186 | CLEAR_ALL_MASK_BITS_DMA16_out EQU 0DCh ; AT+ |
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187 | |
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188 | |
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189 | ; Write All Mask Bits |
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190 | WRITE_ALL_MASK_BITS_DMA8_out EQU 0Fh |
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191 | ALL_MASK_BITS_SET_CH0 EQU (1<<0) |
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192 | ALL_MASK_BITS_SET_CH1 EQU (1<<CHANNEL_1) |
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193 | ALL_MASK_BITS_SET_CH2 EQU (1<<CHANNEL_2) |
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194 | ALL_MASK_BITS_SET_CH3 EQU (1<<CHANNEL_3) |
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195 | WRITE_ALL_MASK_BITS_DMA16_out EQU 0DEh ; AT+ |
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196 | ALL_MASK_BITS_SET_CH4 EQU ALL_MASK_BITS_SET_CH0 |
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197 | ALL_MASK_BITS_SET_CH5 EQU (1<<CHANNEL_5) |
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198 | ALL_MASK_BITS_SET_CH6 EQU (1<<CHANNEL_6) |
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199 | ALL_MASK_BITS_SET_CH7 EQU (1<<CHANNEL_7) |
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200 | |
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201 | |
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202 | %endif ; DMA_CONTROLLER_INC |
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