source: xtideuniversalbios/tags/XTIDE_Universal_BIOS_v1.1.3/Inc/IdeRegisters.inc

Last change on this file was 3, checked in by aitotat, 14 years ago
File size: 4.1 KB
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1; File name     :   IdeRegisters.inc
2; Project name  :   IDE BIOS
3; Created date  :   23.3.2010
4; Last update   :   23.3.2010
5; Author        :   Tomi Tilli
6; Description   :   Equates for IDE registers, flags and commands.
7%ifndef IDEREGISTERS_INC
8%define IDEREGISTERS_INC
9
10; IDE Register offsets from Command Block base port
11REG_IDE_DATA            EQU     0       ; Data Register
12REGR_IDE_ERROR          EQU     1       ; Error Register
13REGW_IDE_FEAT           EQU     1       ; Features Register (ATA1+)
14;REGW_IDE_WRPC          EQU     1       ; Write Precompensation Register (obsolete on ATA1+)
15REG_IDE_CNT             EQU     2       ; Sector Count Register
16REG_IDE_SECT            EQU     3       ; Sector Number Register (LBA 7...0)
17REG_IDE_LBA_LOW         EQU     3       ; LBA Low Register
18REG_IDE_LOCYL           EQU     4       ; Low Cylinder Register (LBA 15...8)
19REG_IDE_LBA_MID         EQU     4       ; LBA Mid Register
20REG_IDE_HICYL           EQU     5       ; High Cylinder Register (LBA 23...16)
21REG_IDE_LBA_HIGH        EQU     5       ; LBA High Register
22REG_IDE_DRVHD           EQU     6       ; Drive and Head Register (LBA 27...24)
23REGR_IDE_ST             EQU     7       ; Status Register
24REGW_IDE_CMD            EQU     7       ; Command Register
25REG_IDE_HIDATA          EQU     8       ; XTIDE Data High Register (actually first Control Block reg)
26
27; IDE Register offsets from Control Block base port
28; (usually Command Block base port + 200h)
29REGR_IDEC_AST           EQU     6       ; Alternate Status Register
30REGW_IDEC_CTRL          EQU     6       ; Device Control Register
31;REGR_IDEC_ADDR         EQU     7       ; Drive Address Register (obsolete on ATA2+)
32
33
34; Bit definitions for IDE Error Register
35FLG_IDE_ERR_BBK         EQU     (1<<7)  ; Bad Block Detected (reserved on ATA2+, command dependent on ATA4+)
36FLG_IDE_ERR_UNC         EQU     (1<<6)  ; Uncorrectable Data Error (command dependent on ATA4+)
37FLG_IDE_ERR_MC          EQU     (1<<5)  ; Media Changed (command dependent on ATA4+)
38FLG_IDE_ERR_IDNF        EQU     (1<<4)  ; ID Not Found (command dependent on ATA4+)
39FLG_IDE_ERR_MCR         EQU     (1<<3)  ; Media Change Request (command dependent on ATA4+)
40FLG_IDE_ERR_ABRT        EQU     (1<<2)  ; Command Aborted
41FLG_IDE_ERR_TK0NF       EQU     (1<<1)  ; Track 0 Not Found (command dependent on ATA4+)
42FLG_IDE_ERR_AMNF        EQU     (1<<0)  ; Address Mark Not Found (command dependent on ATA4+)
43
44; Bit definitions for IDE Drive and Head Select Register
45FLG_IDE_DRVHD_LBA       EQU     (1<<6)  ; LBA Addressing enabled (instead of CHS)
46FLG_IDE_DRVHD_DRV       EQU     (1<<4)  ; Drive Select (0=Master, 1=Slave)
47MASK_IDE_DRVHD_HEAD     EQU     0Fh     ; Head select bits (bits 0...3)
48MASK_IDE_DRVHD_SET      EQU     0A0h    ; Bits that must be set to 1 on ATA1 (reserved on ATA2+)
49
50; Bit definitions for IDE Status Register
51FLG_IDE_ST_BSY          EQU     (1<<7)  ; Busy (other flags undefined when set)
52FLG_IDE_ST_DRDY         EQU     (1<<6)  ; Device Ready
53FLG_IDE_ST_DF           EQU     (1<<5)  ; Device Fault (command dependent on ATA4+)
54FLG_IDE_ST_DSC          EQU     (1<<4)  ; Device Seek Complete (command dependent on ATA4+)
55FLG_IDE_ST_DRQ          EQU     (1<<3)  ; Data Request
56FLG_IDE_ST_CORR         EQU     (1<<2)  ; Corrected Data (obsolete on ATA4+)
57FLG_IDE_ST_IDX          EQU     (1<<1)  ; Index (vendor specific on ATA2+, obsolete on ATA4+)
58FLG_IDE_ST_ERR          EQU     (1<<0)  ; Error
59
60; Bit definitions for IDE Device Control Register
61; Bit 0 must be zero, unlisted bits are reserved.
62FLG_IDE_CTRL_O8H        EQU     (1<<3)  ; Drive has more than 8 heads (pre-ATA only, 1 on ATA1, reserved on ATA2+)
63FLG_IDE_CTRL_SRST       EQU     (1<<2)  ; Software Reset
64FLG_IDE_CTRL_nIEN       EQU     (1<<1)  ; Negated Interrupt Enable (IRQ disabled when set)
65
66
67; Commands for IDE Controller
68;HCMD_RECALIBRATE       EQU     10h     ; Recalibrate
69HCMD_READ_SECT          EQU     20h     ; Read Sectors (with retries)
70HCMD_WRITE_SECT         EQU     30h     ; Write Sectors (with retries)
71HCMD_VERIFY_SECT        EQU     40h     ; Read Verify Sectors (with retries)
72;HCMD_FORMAT            EQU     50h     ; Format track
73HCMD_SEEK               EQU     70h     ; Seek
74;HCMD_DIAGNOSTIC        EQU     90h     ; Execute Device Diagnostic
75HCMD_INIT_DEV           EQU     91h     ; Initialize Device Parameters
76HCMD_READ_MUL           EQU     0C4h    ; Read Multiple (=block)
77HCMD_WRITE_MUL          EQU     0C5h    ; Write Multiple (=block)
78HCMD_SET_MUL            EQU     0C6h    ; Set Multiple Mode (=block size)
79HCMD_ID_DEV             EQU     0ECh    ; Identify Device
80HCMD_SET_FEAT           EQU     0EFh    ; Set Features
81
82; Set Features subcommands
83HFEAT_SET_XFER_MODE     EQU     03h     ; Set transfer mode based on value in Sector Count register
84
85
86%endif ; IDEREGISTERS_INC
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