1 | ; Project name : XTIDE Universal BIOS |
---|
2 | ; Description : IDE Register I/O functions. |
---|
3 | |
---|
4 | ; |
---|
5 | ; XTIDE Universal BIOS and Associated Tools |
---|
6 | ; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2012 by XTIDE Universal BIOS Team. |
---|
7 | ; |
---|
8 | ; This program is free software; you can redistribute it and/or modify |
---|
9 | ; it under the terms of the GNU General Public License as published by |
---|
10 | ; the Free Software Foundation; either version 2 of the License, or |
---|
11 | ; (at your option) any later version. |
---|
12 | ; |
---|
13 | ; This program is distributed in the hope that it will be useful, |
---|
14 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of |
---|
15 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
---|
16 | ; GNU General Public License for more details. |
---|
17 | ; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html |
---|
18 | ; |
---|
19 | |
---|
20 | ; Section containing code |
---|
21 | SECTION .text |
---|
22 | |
---|
23 | ;-------------------------------------------------------------------- |
---|
24 | ; IdeIO_OutputALtoIdeControlBlockRegisterInDL |
---|
25 | ; Parameters: |
---|
26 | ; AL: Byte to output |
---|
27 | ; DL: IDE Control Block Register |
---|
28 | ; DS:DI: Ptr to DPT (in RAMVARS segment) |
---|
29 | ; Returns: |
---|
30 | ; Nothing |
---|
31 | ; Corrupts registers: |
---|
32 | ; BX, DX |
---|
33 | ;-------------------------------------------------------------------- |
---|
34 | IdeIO_OutputALtoIdeControlBlockRegisterInDL: |
---|
35 | %ifdef MODULE_8BIT_IDE |
---|
36 | mov dh, [di+DPT_ATA.bDevice] |
---|
37 | %ifdef MODULE_JRIDE |
---|
38 | test dh, dh |
---|
39 | jnz SHORT .OutputToIoMappedIde |
---|
40 | |
---|
41 | add dx, JRIDE_CONTROL_BLOCK_REGISTER_WINDOW_OFFSET |
---|
42 | jmp SHORT OutputToJrIdeRegister |
---|
43 | .OutputToIoMappedIde: |
---|
44 | %endif ; MODULE_JRIDE |
---|
45 | %endif ; MODULE_8BIT_IDE |
---|
46 | |
---|
47 | mov bl, IDEVARS.wPortCtrl |
---|
48 | jmp SHORT OutputALtoIdeRegisterInDLwithIdevarsOffsetToBasePortInBL |
---|
49 | |
---|
50 | |
---|
51 | ;-------------------------------------------------------------------- |
---|
52 | ; IdeIO_OutputALtoIdeRegisterInDL |
---|
53 | ; Parameters: |
---|
54 | ; AL: Byte to output |
---|
55 | ; DL: IDE Command Block Register |
---|
56 | ; DS:DI: Ptr to DPT (in RAMVARS segment) |
---|
57 | ; Returns: |
---|
58 | ; Nothing |
---|
59 | ; Corrupts registers: |
---|
60 | ; BX, DX |
---|
61 | ;-------------------------------------------------------------------- |
---|
62 | ALIGN JUMP_ALIGN |
---|
63 | IdeIO_OutputALtoIdeRegisterInDL: |
---|
64 | %ifdef MODULE_8BIT_IDE |
---|
65 | mov dh, [di+DPT_ATA.bDevice] |
---|
66 | %ifdef MODULE_JRIDE |
---|
67 | test dh, dh |
---|
68 | jnz SHORT OutputALtoIOmappedIdeRegisterInDL |
---|
69 | |
---|
70 | %if JRIDE_COMMAND_BLOCK_REGISTER_WINDOW_OFFSET & 0FFh = 0 |
---|
71 | mov dh, JRIDE_COMMAND_BLOCK_REGISTER_WINDOW_OFFSET >> 8 |
---|
72 | %else |
---|
73 | add dx, JRIDE_COMMAND_BLOCK_REGISTER_WINDOW_OFFSET |
---|
74 | %endif |
---|
75 | OutputToJrIdeRegister: |
---|
76 | mov bx, dx |
---|
77 | mov [cs:bx], al |
---|
78 | ret |
---|
79 | ALIGN JUMP_ALIGN |
---|
80 | OutputALtoIOmappedIdeRegisterInDL: |
---|
81 | %endif ; MODULE_JRIDE |
---|
82 | %endif ; MODULE_8BIT_IDE |
---|
83 | |
---|
84 | mov bl, IDEVARS.wPort |
---|
85 | OutputALtoIdeRegisterInDLwithIdevarsOffsetToBasePortInBL: |
---|
86 | call GetIdePortToDX |
---|
87 | out dx, al |
---|
88 | ret |
---|
89 | |
---|
90 | |
---|
91 | ;-------------------------------------------------------------------- |
---|
92 | ; IdeIO_InputStatusRegisterToAL |
---|
93 | ; Parameters: |
---|
94 | ; DS:DI: Ptr to DPT (in RAMVARS segment) |
---|
95 | ; Returns: |
---|
96 | ; AL: IDE Status Register contents |
---|
97 | ; Corrupts registers: |
---|
98 | ; BX, DX |
---|
99 | ;-------------------------------------------------------------------- |
---|
100 | ALIGN JUMP_ALIGN |
---|
101 | IdeIO_InputStatusRegisterToAL: |
---|
102 | mov dl, STATUS_REGISTER_in |
---|
103 | ; Fall to IdeIO_InputToALfromIdeRegisterInDL |
---|
104 | |
---|
105 | ;-------------------------------------------------------------------- |
---|
106 | ; IdeIO_InputToALfromIdeRegisterInDL |
---|
107 | ; Parameters: |
---|
108 | ; DL: IDE Register |
---|
109 | ; DS:DI: Ptr to DPT (in RAMVARS segment) |
---|
110 | ; Returns: |
---|
111 | ; AL: Inputted byte |
---|
112 | ; Corrupts registers: |
---|
113 | ; BX, DX |
---|
114 | ;-------------------------------------------------------------------- |
---|
115 | IdeIO_InputToALfromIdeRegisterInDL: |
---|
116 | %ifdef MODULE_8BIT_IDE |
---|
117 | mov dh, [di+DPT_ATA.bDevice] |
---|
118 | %ifdef MODULE_JRIDE |
---|
119 | test dh, dh |
---|
120 | jnz SHORT .InputToALfromIOmappedIdeRegisterInDL |
---|
121 | |
---|
122 | %if JRIDE_COMMAND_BLOCK_REGISTER_WINDOW_OFFSET & 0FFh = 0 |
---|
123 | mov dh, JRIDE_COMMAND_BLOCK_REGISTER_WINDOW_OFFSET >> 8 |
---|
124 | %else |
---|
125 | add dx, JRIDE_COMMAND_BLOCK_REGISTER_WINDOW_OFFSET |
---|
126 | %endif |
---|
127 | mov bx, dx |
---|
128 | mov al, [cs:bx] |
---|
129 | ret |
---|
130 | .InputToALfromIOmappedIdeRegisterInDL: |
---|
131 | %endif ; MODULE_JRIDE |
---|
132 | %endif ; MODULE_8BIT_IDE |
---|
133 | mov bl, IDEVARS.wPort |
---|
134 | call GetIdePortToDX |
---|
135 | in al, dx |
---|
136 | ret |
---|
137 | |
---|
138 | |
---|
139 | ;-------------------------------------------------------------------- |
---|
140 | ; GetIdePortToDX |
---|
141 | ; Parameters: |
---|
142 | ; BL: Offset to port in IDEVARS (IDEVARS.wPort or IDEVARS.wPortCtrl) |
---|
143 | ; DH: Device Type (IDEVARS.bDevice) |
---|
144 | ; DL: IDE Register |
---|
145 | ; DS:DI: Ptr to DPT (in RAMVARS segment) |
---|
146 | ; Returns: |
---|
147 | ; DX: Source/Destination Port |
---|
148 | ; Corrupts registers: |
---|
149 | ; BX |
---|
150 | ;-------------------------------------------------------------------- |
---|
151 | ALIGN JUMP_ALIGN |
---|
152 | GetIdePortToDX: |
---|
153 | %ifdef MODULE_8BIT_IDE |
---|
154 | ; Point CS:BX to IDEVARS |
---|
155 | xor bh, bh |
---|
156 | add bl, [di+DPT.bIdevarsOffset] ; CS:BX now points port address |
---|
157 | |
---|
158 | ; Load port address and check if A0 and A3 address lines need to be reversed |
---|
159 | cmp dh, DEVICE_8BIT_XTIDE_REV1 |
---|
160 | mov dh, bh ; DX now has IDE register offset |
---|
161 | jae SHORT .ReturnUntranslatedPortInDX ; No need to swap address lines |
---|
162 | |
---|
163 | ; Exchange address lines A0 and A3 from DL |
---|
164 | add dx, [cs:bx] ; DX now has port address |
---|
165 | mov bl, dl |
---|
166 | mov bh, MASK_A3_AND_A0_ADDRESS_LINES |
---|
167 | and bh, bl ; BH = 0, 1, 8 or 9, we can ignore 0 and 9 |
---|
168 | jz SHORT .ReturnTranslatedPortInDX ; Jump out since DH is 0 |
---|
169 | xor bh, MASK_A3_AND_A0_ADDRESS_LINES |
---|
170 | jz SHORT .ReturnTranslatedPortInDX ; Jump out since DH was 9 |
---|
171 | and dl, ~MASK_A3_AND_A0_ADDRESS_LINES |
---|
172 | or dl, bh ; Address lines now reversed |
---|
173 | .ReturnTranslatedPortInDX: |
---|
174 | ret |
---|
175 | |
---|
176 | .ReturnUntranslatedPortInDX: |
---|
177 | add dx, [cs:bx] |
---|
178 | ret |
---|
179 | |
---|
180 | %else ; Only standard IDE devices |
---|
181 | xor bh, bh |
---|
182 | add bl, [di+DPT.bIdevarsOffset] ; CS:BX now points port address |
---|
183 | xor dh, dh |
---|
184 | add dx, [cs:bx] ; DX now has port address |
---|
185 | ret |
---|
186 | %endif |
---|