1 | ; Project name : XTIDE Universal BIOS |
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2 | ; Description : IDE Device DMA transfer functions. |
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3 | |
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4 | ; |
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5 | ; XTIDE Universal BIOS and Associated Tools |
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6 | ; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2012 by XTIDE Universal BIOS Team. |
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7 | ; |
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8 | ; This program is free software; you can redistribute it and/or modify |
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9 | ; it under the terms of the GNU General Public License as published by |
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10 | ; the Free Software Foundation; either version 2 of the License, or |
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11 | ; (at your option) any later version. |
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12 | ; |
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13 | ; This program is distributed in the hope that it will be useful, |
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14 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of |
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15 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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16 | ; GNU General Public License for more details. |
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17 | ; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html |
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18 | ; |
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19 | |
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20 | ; Structure containing variables for DMA transfer functions. |
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21 | ; This struct must not be larger than IDEPACK without INTPACK. |
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22 | struc DMAVARS ; Must not be larger than 9 bytes! See IDEPACK in RamVars.inc. |
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23 | .wTotalBytesXferred resb 2 ; 0-1, |
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24 | .wBytesLeftToXfer resb 2 ; 2-3, 0 = 65536 |
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25 | .bbbPhysicalAddress resb 3 ; 4-6, |
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26 | resb 1 ; 7, IDEPACK.bDeviceControl |
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27 | endstruc |
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28 | |
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29 | |
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30 | ; Section containing code |
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31 | SECTION .text |
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32 | |
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33 | ;-------------------------------------------------------------------- |
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34 | ; IdeDmaTransfer_StartWithCommandInAL |
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35 | ; Parameters: |
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36 | ; AL: IDE command that was used to start the transfer |
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37 | ; (all PIO read and write commands including Identify Device) |
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38 | ; ES:SI: Ptr to data buffer (not normalized) |
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39 | ; DS:DI: Ptr to DPT (in RAMVARS segment) |
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40 | ; SS:BP: Ptr to IDEPACK |
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41 | ; Returns: |
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42 | ; AH: INT 13h Error Code |
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43 | ; CX: Number of successfully transferred sectors |
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44 | ; CF: Cleared if success, Set if error |
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45 | ; Corrupts registers: |
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46 | ; AL, BX, DX |
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47 | ;-------------------------------------------------------------------- |
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48 | ALIGN JUMP_ALIGN |
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49 | IdeDmaTransfer_StartWithCommandInAL: |
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50 | ; Initialize DMAVARS |
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51 | xor cx, cx |
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52 | mov [bp+DMAVARS.wTotalBytesXferred], cx |
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53 | mov ch, [bp+IDEPACK.bSectorCount] ; CX = WORDs to transfer |
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54 | shl cx, 1 ; WORDs to BYTEs, 0 = 65536 |
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55 | mov [bp+DMAVARS.wBytesLeftToXfer], cx |
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56 | |
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57 | ; Convert Segment:Offset type pointer to physical address |
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58 | xor bx, bx |
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59 | mov cx, es |
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60 | %rep 4 |
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61 | shl cx, 1 |
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62 | rcl bx, 1 |
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63 | %endrep |
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64 | add cx, si |
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65 | adc bl, bh |
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66 | mov [bp+DMAVARS.bbbPhysicalAddress], cx |
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67 | mov [bp+DMAVARS.bbbPhysicalAddress+2], bl |
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68 | |
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69 | ; Calculate bytes for first page |
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70 | neg cx ; Max number of bytes for first page, 0 = 65536 |
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71 | MIN_U cx, [bp+DMAVARS.wBytesLeftToXfer] |
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72 | |
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73 | ; Are we reading or writing? |
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74 | mov bl, CHANNEL_3 | READ | AUTOINIT_DISABLE | ADDRESS_INCREMENT | DEMAND_MODE ; Assume write command |
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75 | test al, 16 ; Bit 4 is cleared on all the read commands but set on 3 of the 4 write commands |
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76 | jnz SHORT TransferBlockToOrFromXTCF |
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77 | cmp al, COMMAND_WRITE_MULTIPLE |
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78 | je SHORT TransferBlockToOrFromXTCF |
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79 | |
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80 | ; Read command |
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81 | mov bl, CHANNEL_3 | WRITE | AUTOINIT_DISABLE | ADDRESS_INCREMENT | DEMAND_MODE |
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82 | ; Fall to TransferBlockToOrFromXTCF |
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83 | |
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84 | |
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85 | ;-------------------------------------------------------------------- |
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86 | ; TransferBlockToOrFromXTCF |
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87 | ; Parameters: |
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88 | ; BX: Mode byte for DMA Mode Register |
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89 | ; CX: Bytes in first page |
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90 | ; DS:DI: Ptr to DPT (in RAMVARS segment) |
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91 | ; SS:BP: Ptr to DMAVARS |
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92 | ; Returns: |
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93 | ; DS:DI: Ptr to DPT (in RAMVARS segment) |
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94 | ; AH: BIOS Error code |
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95 | ; CX: Number of successfully transferred sectors |
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96 | ; CF: 0 if transfer successful |
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97 | ; 1 if any error |
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98 | ; Corrupts registers: |
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99 | ; AL, BX, DX |
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100 | ;-------------------------------------------------------------------- |
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101 | TransferBlockToOrFromXTCF: |
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102 | ; 8-bit DMA transfers must be done withing 64k physical page. |
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103 | ; We support maximum of 128 sectors (65536 bytes) per one INT 13h call |
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104 | ; so we might need to separate transfer to 2 separate DMA operations. |
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105 | |
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106 | ; Transfer first DMA page |
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107 | call StartDMAtransferForXTCFwithDmaModeInBL |
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108 | jcxz .ReturnNumberOfSectorsXferred ; One page was enough (128 sectors) |
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109 | mov [bp+DMAVARS.wTotalBytesXferred], cx ; Store total BYTEs transferred so far |
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110 | |
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111 | ; Get bytes left to transfer for second DMA page |
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112 | mov ax, [bp+DMAVARS.wBytesLeftToXfer] |
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113 | sub ax, cx |
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114 | jz SHORT .ReturnNumberOfSectorsXferred ; Transfer was within 64k page |
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115 | |
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116 | ; Increment address |
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117 | xchg cx, ax |
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118 | add [bp+DMAVARS.bbbPhysicalAddress], ax |
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119 | adc [bp+DMAVARS.bbbPhysicalAddress+2], bh ; Never sets CF |
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120 | |
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121 | ; Transfer second DMA page if necessary (always less than 64k) |
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122 | call StartDMAtransferForXTCFwithDmaModeInBL |
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123 | add [bp+DMAVARS.wTotalBytesXferred], cx |
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124 | |
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125 | .ReturnNumberOfSectorsXferred: |
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126 | ; Check errors |
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127 | mov bx, TIMEOUT_AND_STATUS_TO_WAIT(TIMEOUT_DRQ, FLG_STATUS_BSY) |
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128 | call IdeWait_PollStatusFlagInBLwithTimeoutInBH |
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129 | jc SHORT .ErrorInTransfer |
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130 | |
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131 | ; Return number of sectors transferred |
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132 | mov cx, [bp+DMAVARS.wTotalBytesXferred] |
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133 | jcxz .FullPageOf128SectorsXferred |
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134 | %ifdef USE_186 |
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135 | shr cx, 9 ; BYTEs to sectors |
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136 | %else |
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137 | xchg cl, ch ; BYTEs to WORDs |
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138 | shr cx, 1 ; WORDs to sectors |
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139 | %endif |
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140 | clc |
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141 | ret |
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142 | |
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143 | .FullPageOf128SectorsXferred: |
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144 | mov cx, 128 |
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145 | ret |
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146 | |
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147 | .ErrorInTransfer: |
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148 | mov cx, 0 ; No way to know how many sectors got transferred |
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149 | ret |
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150 | |
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151 | |
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152 | ;-------------------------------------------------------------------- |
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153 | ; StartDMAtransferForXTCFwithDmaModeInBL |
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154 | ; Parameters: |
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155 | ; BL: Byte for DMA Mode Register |
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156 | ; CX: Number of BYTEs to transfer |
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157 | ; DS:DI: Ptr to DPT (in RAMVARS segment) |
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158 | ; SS:BP: Ptr to DMAVARS |
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159 | ; Returns: |
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160 | ; Nothing |
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161 | ; Corrupts registers: |
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162 | ; AL, DX |
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163 | ;-------------------------------------------------------------------- |
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164 | ALIGN JUMP_ALIGN |
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165 | StartDMAtransferForXTCFwithDmaModeInBL: |
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166 | ; Program 8-bit DMA Controller |
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167 | ; Disable Interrupts and DMA Channel 3 during DMA setup |
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168 | cli ; Disable interrupts |
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169 | mov al, SET_CH3_MASK_BIT |
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170 | out MASK_REGISTER_DMA8_out, al ; Disable DMA Channel 3 |
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171 | |
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172 | ; Set DMA Mode (read or write using channel 3) |
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173 | mov al, bl |
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174 | out MODE_REGISTER_DMA8_out, al |
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175 | |
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176 | ; Set address to DMA controller |
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177 | out CLEAR_FLIPFLOP_DMA8_out, al ; Reset flip-flop to low byte |
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178 | mov ax, [bp+DMAVARS.bbbPhysicalAddress] |
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179 | out BASE_AND_CURRENT_ADDRESS_REGISTER_DMA8_CH3_out, al ; Low byte |
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180 | mov al, ah |
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181 | out BASE_AND_CURRENT_ADDRESS_REGISTER_DMA8_CH3_out, al ; High byte |
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182 | mov al, [bp+DMAVARS.bbbPhysicalAddress+2] |
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183 | out PAGE_DMA8_CH_3, al |
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184 | |
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185 | ; Set number of bytes to transfer (DMA controller must be programmed number of bytes - 1) |
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186 | out CLEAR_FLIPFLOP_DMA8_out, al ; Reset flip-flop to low byte |
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187 | mov ax, cx |
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188 | dec ax ; DMA controller is programmed for one byte less |
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189 | out BASE_AND_CURRENT_COUNT_REGISTER_DMA8_CH3_out, al ; Low byte |
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190 | mov al, ah |
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191 | out BASE_AND_CURRENT_COUNT_REGISTER_DMA8_CH3_out, al ; High byte |
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192 | |
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193 | ; Enable DMA Channel 3 |
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194 | mov al, CLEAR_CH3_MASK_BIT |
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195 | out MASK_REGISTER_DMA8_out, al ; Enable DMA Channel 3 |
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196 | sti ; Enable interrupts |
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197 | |
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198 | |
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199 | ; XT-CF transfers 16 bytes at a time. We need to manually |
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200 | ; start transfer for every block. |
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201 | mov dx, [di+DPT.wBasePort] |
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202 | add dl, XTCF_CONTROL_REGISTER |
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203 | ALIGN JUMP_ALIGN |
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204 | .TransferNextBlock: |
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205 | mov al, RAISE_DRQ_AND_CLEAR_XTCF_XFER_COUNTER |
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206 | cli ; We want no ISR to read DMA Status Register before we do |
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207 | out dx, al ; Transfer up to 16 bytes to/from XT-CF card |
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208 | ; * Here XT-CF sets CPU to wait states during transfer * |
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209 | in al, STATUS_REGISTER_DMA8_in |
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210 | sti |
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211 | test al, FLG_CH3_HAS_REACHED_TERMINAL_COUNT |
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212 | jz SHORT .TransferNextBlock ; All bytes transferred? |
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213 | |
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214 | ; Restore XT-CF to normal operation |
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215 | mov al, XTCF_DMA_MODE |
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216 | out dx, al |
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217 | ret |
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