source: xtideuniversalbios/trunk/XTIDE_Universal_BIOS/Inc/RomVars.inc @ 536

Last change on this file since 536 was 536, checked in by krille_n_@…, 11 years ago

Changes:

  • Added support for the Silicon Valley Computer ADP50L controller (and possibly other IDE controllers from SVC using memory mapped I/O). Please note that this has not been tested in any way since I don't have any of these cards myself (make backups before trying this on drives with important data). Also, *if* it works, make sure it works reliably (stress test the disk system). Some things you should know: 1) Autodetection for this controller has not been added to XTIDECFG, you need to manually select the "SVC ADP50L" controller (and possibly change the BIOS segment address if not using the default of C800h). 2) The memory mapped I/O window is inside the ROM address space of the controller. The XTIDE Universal BIOS currently do not support this so that means you need to use another ROM (for example, an XTIDE or XTCF card or the BOOT ROM of a NIC). This presents another problem, the original ADP50L BIOS needs to be disabled somehow to avoid conflicts. Either pull the ROM chip or disable the BIOS by removing jumper J3. Note, I have no idea if any of this will actually work. It's basically a shot in the dark.
File size: 8.2 KB
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1; Project name  :   XTIDE Universal BIOS
2; Description   :   Defines for ROMVARS struct containing variables stored
3;                   in BIOS ROM.
4
5;
6; XTIDE Universal BIOS and Associated Tools
7; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2013 by XTIDE Universal BIOS Team.
8;
9; This program is free software; you can redistribute it and/or modify
10; it under the terms of the GNU General Public License as published by
11; the Free Software Foundation; either version 2 of the License, or
12; (at your option) any later version.
13;
14; This program is distributed in the hope that it will be useful,
15; but WITHOUT ANY WARRANTY; without even the implied warranty of
16; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17; GNU General Public License for more details.
18; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
19;
20
21%ifndef ROMVARS_INC
22%define ROMVARS_INC
23
24; ROM Variables. Written to the ROM image before flashing.
25struc ROMVARS
26    .wRomSign           resb    2   ; ROM Signature (AA55h)
27    .bRomSize           resb    1   ; ROM size in 512 byte blocks
28    .rgbJump            resb    3   ; First instruction to ROM init (jmp)
29
30    .rgbSign            resb    8   ; Signature for XTIDE Configurator Program
31    .szTitle            resb    31  ; BIOS title string
32    .szVersion          resb    25  ; BIOS version string
33
34    .wFlags             resb    2   ; Word for ROM flags
35    .wDisplayMode       resb    2   ; Display mode for boot menu
36    .wBootTimeout       resb    2   ; Boot Menu selection timeout in system timer ticks
37    .bIdeCnt            resb    1   ; Number of available IDE controllers
38    .bBootDrv           resb    1   ; Default drive to boot from
39    .bMinFddCnt         resb    1   ; Minimum number of Floppy Drives
40    .bStealSize         resb    1   ; Number of 1kB blocks stolen from 640kB base RAM
41    .bIdleTimeout       resb    1   ; Standby timer value
42
43    .ideVarsBegin:
44    .ideVars0           resb    IDEVARS_size
45    .ideVars1           resb    IDEVARS_size
46    .ideVars2           resb    IDEVARS_size
47    .ideVars3           resb    IDEVARS_size
48
49%ifdef MODULE_SERIAL
50    .ideVarsSerialAuto  resb    IDEVARS_size
51%endif
52
53    .ideVarsEnd:
54endstruc
55
56%ifndef CHECK_FOR_UNUSED_ENTRYPOINTS
57    %if ROMVARS.ideVarsEnd & 0xff00 <> 0
58        %error ".ideVars structures must fit within the first 256 bytes of the ROM image"
59    %endif
60    %if (ROMVARS.ideVarsEnd - ROMVARS.ideVarsBegin) = 0
61        %error "there must be at least one .ideVars structure, it would be bizarre if this were not true, but it is assumed in the ah0h reset code."
62    %endif
63%endif
64
65NUMBER_OF_IDEVARS                   EQU ((ROMVARS.ideVarsEnd - ROMVARS.ideVarsBegin) / IDEVARS_size)
66
67; Bit defines for ROMVARS.wFlags
68FLG_ROMVARS_FULLMODE                EQU (1<<0)  ; Full operating mode (steals base RAM, supports EBIOS etc.)
69FLG_ROMVARS_SERIAL_SCANDETECT       EQU (1<<3)  ; Scan COM ports at the end of drive detection.  Can also be invoked
70                                                ; by holding down the ALT key at the end of drive detection.
71                                                ; (Conveniently, this is 8, a fact we exploit when testing the bit)
72
73; Here in case the configuration needs to know functionality is present
74FLG_ROMVARS_MODULE_FEATURE_SETS         EQU (1<<5)
75FLG_ROMVARS_MODULE_8BIT_IDE             EQU (1<<6)
76FLG_ROMVARS_MODULE_8BIT_IDE_ADVANCED    EQU (1<<7)
77FLG_ROMVARS_MODULE_ADVANCED_ATA         EQU (1<<8)
78FLG_ROMVARS_MODULE_BOOT_MENU            EQU (1<<9)
79FLG_ROMVARS_MODULE_EBIOS                EQU (1<<10)
80FLG_ROMVARS_MODULE_HOTKEYS              EQU (1<<11)
81FLG_ROMVARS_MODULE_IRQ                  EQU (1<<12)
82FLG_ROMVARS_MODULE_SERIAL               EQU (1<<13)
83FLG_ROMVARS_MODULE_SERIAL_FLOPPY        EQU (1<<14)
84FLG_ROMVARS_MODULE_STRINGS_COMPRESSED   EQU (1<<15)
85
86
87; Boot Menu Display Modes (see Assembly Library Display.inc for standard modes)
88DEFAULT_TEXT_MODE       EQU 4
89
90
91; Controller specific variables
92struc IDEVARS
93;;; Word 0
94    .wSerialPortAndBaud:                    ; Serial connection port (low, divided by 4) and baud rate divisor (high)
95    .wBasePort:                             ; IDE Base Port for Command Block (usual) Registers
96    .bSerialPort                resb    1
97    .bSerialBaud                resb    1
98
99;;; Word 1
100    .wControlBlockPort:
101    .bXTCFcontrolRegister:                  ; XT-CF autodetects ports
102    .bSerialUnused              resb    1   ; IDE Base Port for Control Block Registers
103
104    .wSerialCOMPortCharAndDevice:           ; In DetectPrint, we grab the COM Port char and Device at the same time
105    .bSerialCOMPortChar         resb    1   ; Serial connection COM port number/letter
106
107;;; Word 2
108    .bDevice                    resb    1   ; Device type
109    .bIRQ                       resb    1   ; Interrupt Request Number
110
111;;; And more...
112    .drvParamsMaster            resb    DRVPARAMS_size
113    .drvParamsSlave             resb    DRVPARAMS_size
114endstruc
115
116%ifndef CHECK_FOR_UNUSED_ENTRYPOINTS
117    %if IDEVARS.bSerialCOMPortChar+1 != IDEVARS.bDevice
118        %error "IDEVARS.bSerialCOMPortChar needs to come immediately before IDEVARS.bDevice so that both bytes can be fetched at the same time inside DetectPrint.asm"
119    %endif
120%endif
121
122STANDARD_CONTROL_BLOCK_OFFSET           EQU     200h
123XTIDE_CONTROL_BLOCK_OFFSET              EQU     8h
124XTCF_CONTROL_BLOCK_OFFSET               EQU     10h
125ADP50L_CONTROL_BLOCK_OFFSET             EQU     10h
126
127; Default values for Port and PortCtrl, shared with the configurator
128;
129DEVICE_XTIDE_DEFAULT_PORT               EQU     300h
130DEVICE_XTIDE_DEFAULT_PORTCTRL           EQU     (DEVICE_XTIDE_DEFAULT_PORT + XTIDE_CONTROL_BLOCK_OFFSET)
131
132DEVICE_ATA_PRIMARY_PORT                 EQU     1F0h
133DEVICE_ATA_PRIMARY_PORTCTRL             EQU     (DEVICE_ATA_PRIMARY_PORT + STANDARD_CONTROL_BLOCK_OFFSET)
134
135DEVICE_ATA_SECONDARY_PORT               EQU     170h
136DEVICE_ATA_SECONDARY_PORTCTRL           EQU     (DEVICE_ATA_SECONDARY_PORT + STANDARD_CONTROL_BLOCK_OFFSET)
137
138DEVICE_ATA_TERTIARY_PORT                EQU     1E8h
139DEVICE_ATA_TERTIARY_PORTCTRL            EQU     (DEVICE_ATA_TERTIARY_PORT + STANDARD_CONTROL_BLOCK_OFFSET)
140
141DEVICE_ATA_QUATERNARY_PORT              EQU     168h
142DEVICE_ATA_QUATERNARY_PORTCTRL          EQU     (DEVICE_ATA_QUATERNARY_PORT + STANDARD_CONTROL_BLOCK_OFFSET)
143
144
145; Device types for IDEVARS.bDevice
146; IDE Devices are grouped so device numbers cannot be changed without modifying code elsewhere!
147;
148COUNT_OF_STANDARD_IDE_DEVICES           EQU 2   ; 16- and 32-bit controllers
149COUNT_OF_8BIT_IDE_DEVICES               EQU 8
150COUNT_OF_ALL_IDE_DEVICES                EQU (COUNT_OF_8BIT_IDE_DEVICES + COUNT_OF_STANDARD_IDE_DEVICES)
151; Standard port mapped I/O
152DEVICE_16BIT_ATA                        EQU (0<<1)
153DEVICE_32BIT_ATA                        EQU (1<<1)
154DEVICE_8BIT_ATA                         EQU ((COUNT_OF_STANDARD_IDE_DEVICES+0)<<1)  ; 16- or 32-bit controller in 8-bit mode
155DEVICE_8BIT_XTIDE_REV1                  EQU ((COUNT_OF_STANDARD_IDE_DEVICES+1)<<1)
156; Address lines A0 and A3 are swapped
157DEVICE_8BIT_XTIDE_REV2                  EQU ((COUNT_OF_STANDARD_IDE_DEVICES+2)<<1)  ; Or rev 1 with swapped A0 and A3
158; IDE Register offsets are SHL 1
159DEVICE_8BIT_XTCF_PIO8                   EQU ((COUNT_OF_STANDARD_IDE_DEVICES+3)<<1)  ; XT-CF using 8-bit PIO mode
160DEVICE_8BIT_XTCF_DMA                    EQU ((COUNT_OF_STANDARD_IDE_DEVICES+4)<<1)  ; XT-CF using DMA
161DEVICE_8BIT_XTCF_MEMMAP                 EQU ((COUNT_OF_STANDARD_IDE_DEVICES+5)<<1)  ; XT-CF using Memory Mapped transfers (not I/O)
162; Memory Mapped I/O
163DEVICE_8BIT_JRIDE_ISA                   EQU ((COUNT_OF_STANDARD_IDE_DEVICES+6)<<1)  ; JR-IDE/ISA (Memory Mapped I/O)
164DEVICE_8BIT_ADP50L                      EQU ((COUNT_OF_STANDARD_IDE_DEVICES+7)<<1)  ; SVC ADP50L (Memory Mapped I/O)
165; Virtual devices
166DEVICE_SERIAL_PORT                      EQU (COUNT_OF_ALL_IDE_DEVICES<<1)
167
168
169
170; Master/Slave drive specific parameters
171struc DRVPARAMS
172    .wFlags         resb    2   ; Drive flags
173    .dwMaximumLBA:              ; User specified maximum number of sectors
174    .wCylinders     resb    2   ; User specified cylinders (1...16383)
175    .wHeadsAndSectors:
176    .bHeads         resb    1   ; User specified Heads (1...16)
177    .bSect          resb    1   ; User specified Sectors per track (1...63)
178endstruc
179
180; Bit defines for DRVPARAMS.wFlags
181MASK_DRVPARAMS_WRITECACHE       EQU (3<<0)  ; Bits 0...1, Drive internal write cache settings (must start at bit 0)
182    DEFAULT_WRITE_CACHE             EQU 0   ; Must be 0
183    DISABLE_WRITE_CACHE             EQU 1
184    ENABLE_WRITE_CACHE              EQU 2
185MASK_DRVPARAMS_TRANSLATEMODE    EQU (3<<TRANSLATEMODE_FIELD_POSITION)   ; Bits 2...3, Position shared with DPT
186    TRANSLATEMODE_FIELD_POSITION    EQU 2
187    TRANSLATEMODE_NORMAL            EQU 0   ; Must be zero
188    TRANSLATEMODE_LARGE             EQU 1
189    TRANSLATEMODE_ASSISTED_LBA      EQU 2   ; 28-bit or 48-bit LBA
190    TRANSLATEMODE_AUTO              EQU 3   ; Only available in ROMVARS, not in DPTs
191FLG_DRVPARAMS_BLOCKMODE         EQU (1<<4)  ; Enable Block mode transfers
192FLG_DRVPARAMS_USERCHS           EQU (1<<5)  ; User specified P-CHS values
193    MAX_USER_CYLINDERS              EQU 16383
194    MAX_USER_HEADS                  EQU 16
195    MAX_USER_SECTORS_PER_TRACK      EQU 63
196FLG_DRVPARAMS_USERLBA           EQU (1<<6)  ; User specified LBA value
197    MIN_USER_LBA_COUNT              EQU ((MAX_USER_CYLINDERS*MAX_USER_HEADS*MAX_USER_SECTORS_PER_TRACK)+1)
198    MAX_USER_LBA_COUNT              EQU ((2^28)-1)
199
200
201%endif ; ROMVARS_INC
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