source: xtideuniversalbios/trunk/XTIDE_Universal_BIOS/Inc/CustomDPT.inc @ 150

Last change on this file since 150 was 150, checked in by aitotat, 13 years ago

Changes to XTIDE Universal BIOS:

  • Redesigned Disk Parameter Tables.
  • Code generalizations for supporting non-IDE devices in the future.
File size: 2.4 KB
Line 
1; Project name  :   XTIDE Universal BIOS
2; Description   :   Defines for DPT structs containing custom
3;                   Disk Parameter Table used by this BIOS.
4%ifndef CUSTOMDPT_INC
5%define CUSTOMDPT_INC
6
7; Base DPT for all device types
8struc DPT   ; 8 bytes
9    ; General Disk Parameter Table related
10    .wFlags                     resb    2
11    .bIdevarsOffset             resb    1   ; Offset to IDEVARS for this drive
12
13    ; L-CHS to P-CHS and L-CHS to LBA28 conversion related
14    .bLchsHeads                 resb    1   ; Number of L-CHS Heads (1...255)
15
16    ; IDE Drive related
17    .wPchsCylinders             resb    2   ; Number of P-CHS (IDE) Cylinders (1...16383)
18    .wPchsHeadsAndSectors:
19    .bPchsHeads                 resb    1   ; Number of P-CHS (IDE) Heads (1...16)
20    .bPchsSectors               resb    1   ; Number of P-CHS (IDE) Sectors per Track (1...63)
21endstruc
22
23; DPT for ATA devices
24struc DPT_ATA   ; 8 + 2 bytes = 10 bytes
25    .dpt                        resb    DPT_size
26
27    ; Block size is specified in sectors (1, 2, 4, 8, 16, 32 or 64).
28    ; 128 is not allowed to prevent offset overflow during data transfer.
29    .wSetAndMaxBlock:
30    .bSetBlock                  resb    1   ; Current block size (at least 1)
31    .bMaxBlock                  resb    1   ; Maximum block size, 0 = block mode not supported
32endstruc
33
34LARGEST_DPT_SIZE                EQU     DPT_ATA_size
35
36
37; Bit definitions for DPT.wFlags
38MASK_DPT_CHS_SHIFT_COUNT        EQU (7<<0)  ; Bits 0...3, P-CHS to L-CHS bit shift count (0...4)
39FLG_DPT_SLAVE                   EQU FLG_DRVNHEAD_DRV    ; (1<<4), Drive is slave drive
40MASK_DPT_ADDRESSING_MODE        EQU (3<<5)  ; Bits 5..6, Addressing Mode (bit 6 == FLG_DRVNHEAD_LBA)
41FLG_DPT_ENABLE_IRQ              EQU (1<<7)
42FLG_DPT_REVERSED_A0_AND_A3      EQU (1<<8)  ; XTIDE mod, Address lines 0 and 3 reversed
43FLG_DPT_SERIAL_DEVICE           EQU (1<<9)  ; Serial Port Device
44FLG_DPT_BLOCK_MODE_SUPPORTED    EQU (1<<10) ; Use block transfer commands
45
46FLG_DPT_RESET_nDRDY             EQU (1<<12) ; Drive ready to accept commands
47FLG_DPT_RESET_nINITPRMS         EQU (1<<13) ; Initialize Device Parameters successfull
48FLG_DPT_RESET_nRECALIBRATE      EQU (1<<14) ; Recalibrate successfull
49FLG_DPT_RESET_nSETBLOCK         EQU (1<<15) ; Initialize Block Mode successfull
50MASK_DPT_RESET                  EQU 0F000h
51
52; Addressing modes for DPT.wFlags
53ADDRESSING_MODE_FIELD_POSITION  EQU     5
54ADDRESSING_MODE_LCHS            EQU     0   ; L-CHS Addressing Mode (NORMAL in many other BIOSes)
55ADDRESSING_MODE_PCHS            EQU     1   ; P-CHS Addressing Mode (LARGE in many other BIOSes)
56ADDRESSING_MODE_LBA28           EQU     2   ; 28-bit LBA Addressing Mode
57ADDRESSING_MODE_LBA48           EQU     3   ; 48-bit LBA Addressing Mode
58
59
60%endif ; CUSTOMDPT_INC
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