[363] | 1 | ; Project name : XTIDE Universal BIOS |
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| 2 | ; Description : QDI Vision QD6500 and QD6580 VLB IDE controller |
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| 3 | ; specifications. |
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| 4 | ; |
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| 5 | ; Specifications can be found at http://www.ryston.cz/petr/vlb/vlbidechips.html |
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| 6 | ; QD6580 DOS Driver Analysis: http://www.ryston.cz/petr/qd/dos37.html |
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[376] | 7 | |
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| 8 | ; |
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[526] | 9 | ; XTIDE Universal BIOS and Associated Tools |
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| 10 | ; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2013 by XTIDE Universal BIOS Team. |
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[376] | 11 | ; |
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| 12 | ; This program is free software; you can redistribute it and/or modify |
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| 13 | ; it under the terms of the GNU General Public License as published by |
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| 14 | ; the Free Software Foundation; either version 2 of the License, or |
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| 15 | ; (at your option) any later version. |
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[526] | 16 | ; |
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[376] | 17 | ; This program is distributed in the hope that it will be useful, |
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| 18 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 19 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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[526] | 20 | ; GNU General Public License for more details. |
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[376] | 21 | ; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html |
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| 22 | ; |
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| 23 | |
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[363] | 24 | %ifndef VISION_INC |
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| 25 | %define VISION_INC |
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| 26 | |
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| 27 | ; Possible base addresses for QD6500 and QD6580 |
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| 28 | QD65XX_BASE_PORT EQU 30h |
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[540] | 29 | QD65XX_ALTERNATIVE_BASE_PORT EQU 0B0h ; This is the default setting but Intel PIIX4 South Bridge |
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[558] | 30 | ; (and likely other PCI chipsets as well) mirror PIC registers here |
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[363] | 31 | |
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| 32 | ; Vision Register offsets from QD chip base port |
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| 33 | QD6500_IDE_TIMING_REGISTER EQU 0 |
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| 34 | QD6580_PRIMARY_IDE_TIMING_REGISTER EQU 0 ; QD6500 has only one channel |
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| 35 | QD65XX_CONFIG_REGISTER_in EQU 1 |
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| 36 | QD6580_SECONDARY_IDE_TIMING_REGISTER EQU 2 ; Same definitions as Primary IDE Timing Register |
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| 37 | QD6580_CONTROL_REGISTER EQU 3 |
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| 38 | |
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| 39 | |
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| 40 | ; Bit definitions for QD65xx IDE Timing Register(s) |
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| 41 | MASK_QD6500IDE_ACTIVE_TIME EQU 7h ; Active time in VLB clocks (bits 0...2) |
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| 42 | ; 000b = 8 clocks (<= 33 MHz), 9 clocks (>33 MHz) |
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| 43 | ; 111b = 1 clock (<= 33 MHz), 2 clocks (>33 MHz) |
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| 44 | MASK_QD6580IDE_ACTIVE_TIME EQU 0Fh ; Active time in VLB clocks (bits 0...3) |
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| 45 | ; 0000b = 17 clocks, 1111b = 2 clocks |
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| 46 | |
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| 47 | MASK_QD6500IDE_RECOVERY_TIME EQU 0F0h ; Recovery time in VLB clocks (bits 4...7) |
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| 48 | ; 0000b = 18 clocks (<= 33 MHz), 15 clocks (>33 MHz) |
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| 49 | ; 1111b = 3 clocks (<= 33 MHz), 0 clocks (>33 MHz) |
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| 50 | MASK_QD6580IDE_RECOVERY_TIME EQU MASK_QD6500IDE_RECOVERY_TIME |
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| 51 | ; 0000b = 15 clocks, 1101b = 2 clocks |
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| 52 | POSITON_QD65XXIDE_RECOVERY_TIME EQU 4 |
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| 53 | |
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| 54 | |
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| 55 | ; Bit definitions for QD65xx Config Register (read only) |
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| 56 | FLG_QDCONFIG_PRIMARY_IDE EQU (1<<0) ; IDE Controller Base Address |
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| 57 | ; 0 = 170h, 1 = 1F0h |
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| 58 | FLG_QDCONFIG_ALTERNATIVE_BASE EQU (1<<1) ; QD Vision Controller Base Address |
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| 59 | ; 0 = 30h, 1 = B0h |
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| 60 | FLG_QDCONFIG_ID3 EQU (1<<2) ; VLB bus speed |
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| 61 | ; 0 = > 33 MHz, 1 = <= 33 MHz |
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| 62 | FLG_QDCONFIG_QD6500STATUS EQU (1<<3) ; QD6500 Enabled/Disabled status |
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| 63 | ; 0 = Enabled, 1 = Disabled |
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| 64 | MASK_QDCONFIG_CONTROLLER_ID EQU 0F0h ; QDI Vision Controller Identification nibble |
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| 65 | |
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| 66 | ; QDI Vision Controller Identification nibbles |
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| 67 | ID_QD6500 EQU 1100b |
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| 68 | ID_QD6580 EQU 1010b |
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| 69 | ID_QD6580_ALTERNATE EQU 0101b |
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| 70 | |
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| 71 | |
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| 72 | ; Bit definitions for QD6580 Control Register |
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| 73 | FLG_QDCONTROL_SECONDARY_DISABLED_in EQU (1<<0) ; 0 = Primary and Secondary IDE enabled (Primary at 1F0h and Secondary at 170h) |
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| 74 | ; 1 = Only Primary IDE enabled (always at 1F0h) |
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| 75 | FLG_QDCONTROL_HDONLY_in EQU (1<<1) ; 0 = Hard drive or ATAPI device |
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| 76 | ; 1 = Hard drives only |
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| 77 | FLG_QDCONTROL_NONATAPI EQU (1<<7) ; Set to 1 for non-ATAPI devices (hard drives, |
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| 78 | ; probably Read ahead and/or post-write control?) |
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| 79 | MASK_QDCONTROL_FLAGS_TO_SET EQU 01011111b ; Bits that must be set when writing the Control Register |
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| 80 | |
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| 81 | |
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| 82 | |
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| 83 | ; Minimum and Maximum Active and Recovery Time Values |
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| 84 | QD6500_MAX_ACTIVE_TIME_CLOCKS EQU 8 ; VLB clocks |
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| 85 | QD6500_MIN_ACTIVE_TIME_CLOCKS EQU 1 ; VLB clocks |
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| 86 | QD6580_MAX_ACTIVE_TIME_CLOCKS EQU 17 ; VLB clocks |
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| 87 | QD6580_MIN_ACTIVE_TIME_CLOCKS EQU 2 ; VLB clocks |
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| 88 | QD65xx_MAX_RECOVERY_TIME_CLOCKS EQU 15 ; VLB clocks |
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| 89 | QD65xx_MIN_RECOVERY_TIME_CLOCKS EQU 2 ; VLB clocks |
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| 90 | |
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| 91 | |
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| 92 | ; Cycle times for different VLB bus clocks |
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| 93 | VLB_33MHZ_CYCLE_TIME EQU 30 ; ns |
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| 94 | VLB_40MHZ_CYCLE_TIME EQU 25 ; ns |
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| 95 | |
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| 96 | |
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| 97 | %endif ; VISION_INC |
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