| 1 | ; Project name : XTIDE Universal BIOS |
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| 2 | ; Description : Promise PDC 20230-C and 20630 VLB IDE controller |
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| 3 | ; specifications. |
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| 4 | ; |
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| 5 | ; Specifications can be found at |
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| 6 | |
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| 7 | ; |
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| 8 | ; XTIDE Universal BIOS and Associated Tools |
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| 9 | ; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2013 by XTIDE Universal BIOS Team. |
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| 10 | ; |
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| 11 | ; This program is free software; you can redistribute it and/or modify |
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| 12 | ; it under the terms of the GNU General Public License as published by |
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| 13 | ; the Free Software Foundation; either version 2 of the License, or |
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| 14 | ; (at your option) any later version. |
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| 15 | ; |
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| 16 | ; This program is distributed in the hope that it will be useful, |
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| 17 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 18 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 19 | ; GNU General Public License for more details. |
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| 20 | ; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html |
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| 21 | ; |
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| 22 | |
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| 23 | %ifndef PDC20x30_INC |
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| 24 | %define PDC20x30_INC |
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| 25 | |
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| 26 | |
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| 27 | ; SECTOR_COUNT_REGISTER in programming mode |
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| 28 | FLG_PDCSCR_UNKNOWN_BIT7 EQU (1<<7) ; Set to 1 for speed setting 7 of device 0 or 1 |
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| 29 | FLG_PDCSCR_ID3 EQU (1<<6) ; VLB bus speed: 0 > 33 MHz, 1 <= 33 MHz |
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| 30 | POS_PDCSCR_DEV0SPEED EQU 3 |
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| 31 | MASK_PDCSCR_DEV0SPEED EQU (7<<POS_PDCSCR_DEV0SPEED) ; 0 to 7 |
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| 32 | MASK_PDCSCR_DEV1SPEED EQU (7<<0) ; 0 to 7 |
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| 33 | |
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| 34 | |
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| 35 | ; LOW_CYLINDER_REGISTER in programming mode |
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| 36 | ; This is only on PDC 20630! |
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| 37 | FLG_PDCLCR_DEV0SPEED_BIT4 EQU (1<<7) ; Possibly speed bit 4 (speed settings 8 to 15)? |
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| 38 | FLG_PDCLCR_DEV1SPEED_BIT4 EQU (1<<6) ; Same as above but for device 1 |
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| 39 | FLG_PDCLCR_DEV0IORDY EQU (1<<5) ; Not sure about this |
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| 40 | FLG_PDCLCR_DEV1IORDY EQU (1<<4) ; Same as above but for device 15 |
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| 41 | FLG_PDCLCR_ENABLE_EXTRA_REGISTERS EQU (1<<3) |
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| 42 | |
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| 43 | |
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| 44 | ; PDC 20630 specific registers mapped after IDE registers |
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| 45 | PDC20630_INDEX_REGISTER EQU 8 ; 1F8h |
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| 46 | PDC20630_DATA_REGISTER EQU 9 ; 1F9h |
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| 47 | |
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| 48 | ; PDC 20630 registers to access through index and data register |
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| 49 | PDCREG0_TIMING_OF_DEV0_LOW EQU 0 ; Low, high, what timings? |
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| 50 | PDCREG1_TIMING_OF_DEV0_HIGH EQU 1 |
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| 51 | PDCREG2_TIMING_OF_DEV1_LOW EQU 2 |
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| 52 | PDCREG3_TIMING_OF_DEV1_HIGH EQU 3 |
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| 53 | PDCREG7_STATUS EQU 7 |
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| 54 | |
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| 55 | FLG_PDCSTATUS_DMA_ERROR EQU (1<<4) ; ? |
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| 56 | FLG_PDCSTATUS_DMA_READ_COMPLETED EQU (1<<1) ; ? |
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| 57 | FLG_PDCSTATUS_DMA_WRITE_COMPLETED EQU (1<<0) ; ? |
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| 58 | |
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| 59 | |
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| 60 | %endif ; PDC20x30_INC |
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