source: xtideuniversalbios/trunk/Assembly_Library/Inc/Delay.inc @ 567

Last change on this file since 567 was 567, checked in by krille_n_@…, 10 years ago

Changes:

  • Renamed MODULE_FEATURE_SETS to MODULE_POWER_MANAGEMENT.
  • Renamed MODULE_VERY_LATE_INITIALIZATION to MODULE_VERY_LATE_INIT and removed it from the official builds.
  • Removed the code that skips detection of slave drives on XT-CF controllers since slave drives can be used with Lo-tech ISA CompactFlash boards.
  • Added autodetection of the SVC ADP50L controller to XTIDECFG.
  • The autodetection of XT-CF controllers now requires MODULE_8BIT_IDE_ADVANCED in the loaded BIOS.
  • Fixed a bug in XTIDECFG from r502 where the "Base (cmd block) address" menu option would be displayed when a serial device was selected as the IDE controller.
  • XTIDECFG would display the "Enable interrupt" menu option for the XTIDE r1 but not for the XTIDE r2. It's now displayed for both controller types.
  • Disabled the "Internal Write Cache" menu option in the Master/Slave Drive menus for serial device type drives.
  • Optimizations and other fixes.
File size: 1.7 KB
Line 
1; Project name  :   Assembly Library
2; Description   :   Delay macros.
3%ifndef DELAY_INC
4%define DELAY_INC
5
6;--------------------------------------------------------------------
7; Clears prefetch queue by jumping to next instruction.
8; This delays much more than nop instruction of fast systems.
9;
10; JMP_DELAY
11;   Parameters
12;       Nothing
13;   Returns:
14;       Nothing
15;   Corrupts registers:
16;       Nothing
17;--------------------------------------------------------------------
18%macro JMP_DELAY 0
19    jmp     SHORT %%NextInstruction
20%%NextInstruction:
21%endmacro
22
23
24;--------------------------------------------------------------------
25; Mimimun delays (without fetching) with some CPU architectures:
26;   8088/8086:  17 cycles for jump + 5 cycles for last comparison
27;   286:        10 cycles for jump + 4 cycles for last comparison
28;   386:        13 cycles for jump + ? cycles for last comparison
29;   486:         7 cycles for jump + 6 cycles for last comparison
30;
31; LOOP instruction uses two bytes so aligned fetching will require:
32;   8088:       8 cycles (two BYTE reads)
33;   8086:       4 cycles (one WORD read)
34;   286:        2 cycles + wait states (usually 1)
35;   386:        ?
36;   486:        Fetched only once to internal cache
37;
38; DELAY_WITH_LOOP_INSTRUCTION_NA    ; No JUMP_ALIGN
39; DELAY_WITH_LOOP_INSTRUCTION
40;   Parameters
41;       CX:     Loop iterations (0 is maximum delay with 65536 iterations)
42;   Returns:
43;       CX:     Zero
44;   Corrupts registers:
45;       Nothing
46;--------------------------------------------------------------------
47%macro DELAY_WITH_LOOP_INSTRUCTION_NA 0
48%%StartOfLoop:
49    loop    %%StartOfLoop
50%endmacro
51
52%macro DELAY_WITH_LOOP_INSTRUCTION 0
53ALIGN JUMP_ALIGN
54%%StartOfLoop:
55    loop    %%StartOfLoop
56%endmacro
57
58
59%endif ; DELAY_INC
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